DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 3

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

1 0 FDDI Chip Set Overview
National Semiconductor’s next generation FDDI 2-chip set
consists of two components as shown in Figure 1-1 The
PLAYER
CRD
Distribution Device and DP83251 55 PLAYER
Layer Controller In addition the PLAYER
enhanced SMT support
National Semiconductor’s FDDI TP-PMD Solutions consist
of two components the DP83222 CYCLONE
Pair FDDI Stream Cipher Device and the DP83223A
TWISTER
For more information on the other devices of the chip set
consult the appropriate datasheets and application notes
1 1 FDDI 2-CHIP SET
DP83256 56-AP 57 PLAYER
Device Physical Layer Controller
The PLAYER
(PHY) protocol as defined by the ANSI FDDI PHY X3T9 5
standard
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
In addition the DP83257 contains the additional PHY Da-
ta request and PHY Data indicate ports required for con-
centrators and dual attach dual path stations
Single chip FDDI Physical Layer (PHY) solution
Integrated Digital Clock Recovery Module provides en-
hanced tracking and greater lock acquisition range
Integrated Clock Generation Module provides all neces-
sary clock signals for an FDDI system from an external
12 5 MHz reference
Alternate PMD Interface (DP83256-AP 57) supports
UTP twisted pair FDDI PMDs with no external clock re-
covery or clock generation functions required
No External Filter Components
Connection Management (CMT) Support (LEM TNE
PC React CF React Auto Scrubbing)
Full on-chip configuration switch
Low Power CMOS-BIPOLAR design using a single 5V
supply
Full duplex operation with through parity
Separate management interface (Control Bus)
Selectable Parity on PHY-MAC Interface and Control
Bus Interface
Two levels of on-chip loopback
4B 5B encoder decoder
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detector generator
Supports single attach stations dual attach stations
and concentrators with no external logic
DP83256 56-AP for SAS DAS single path stations
P83257 for SAS DAS single dual path stations
TM
Clock Recovery Device DP83241 CDD
a
TM
device integrates the features of the DP83231
Twisted Pair FDDI Transceiver Device
a
device implements the Physical Layer
a
device contains
a
TM
TM
TM
Physical
Twisted
Clock
3
DP83266 MACSI
Access Controller and System
Interface
The DP83266 Media Access Controller and System Inter-
face (MACSI) implements the ANSI X3T9 5 Standard Media
Access Control (MAC) protocol for operation in an FDDI
token ring and provides a comprehensive System Interface
The MACSI device transmits receives repeats and strips
tokens and frames It produces and consumes optimized
data structures for efficient data transfer Full duplex archi-
tecture with through parity allows diagnostic transmission
and self testing for error isolation in point-to-point connec-
tions
The MACSI device includes the functionality of both the
DP83261 BMAC device and the DP83265 BSI-2 device with
additional enhancements for higher performance and reli-
ability
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Over 9 Kbytes of on-chip FIFO
5 DMA Channels (2 Output and 3 Input)
12 5 MHz to 33 MHz operation
Full duplex operation with through parity
Real-time VOID frame stripping indicator for bridges
On-chip Address bit swapping capability
32-bit wide Address Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit
words
Receive frame filtering services
Frame-per-Page mode controllable on each DMA
channel
Demultiplexed Addresses supported on ABus
New multicast address matching
ANSI X3T9 5 MAC standard defined ring service op-
tions
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
Supports Individual Group Short Long and External
Addressing
Generates Beacon Claim and Void frames
Extensive ring and station statistics gathering
Extension for MAC level bridging
Enhanced SBus compatibility
Interfaces to DRAMs or directly to system bus
Supports frame Header Info splitting
Programmable Big or Little Endian alignment
TM
Device Media