AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 48

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

48
If an SMI occurs and it does not trap an I/O instruction,
the contents of the I/O address and R/W bit are unpre-
dictable and should not be used.
7.7.6 SMM Base Relocation
The Am5
ter, SMBASE. The SMRAM address space can be mod-
ified by changing the SMBASE register before exiting
an SMI handler routine. SMBASE can be changed to
any 32K-aligned value. (Values that are not 32K-aligned
cause the CPU to enter the shutdown state when exe-
cuting the RSM instruction.) SMBASE is set to the de-
fault value of 30000h on RESET. If SMBASE is changed
by an SMI handler, all subsequent SMI requests initiate
a state save at the new SMBASE.
The SMBASE slot in the SMM state save area indicates
and changes the SMI jump vector location and SMRAM
save area. When bit 17 of the SMM Revision Identifier
is set, then this feature exists and the SMRAM base and
consequently, the jump vector, are as indicated by the
SMM Base slot (see Figure 30). During the execution
of the RSM instruction, the CPU reads this slot and ini-
tializes the CPU to use the new SMBASE during the
next SMI. During an SMI, the CPU does its context save
to the new SMRAM area pointed to by the SMBASE,
stores the current SMBASE in the SMM Base slot (offset
7EF8h), and then starts execution of the new jump vec-
tor based on the current SMBASE (see Figure 31).
The SMBASE must be a 32-Kbyte aligned, 32-bit integer
that indicates a base address for the SMRAM context
save area and the SMI jump vector. For example, when
the processor first powers up, the range for the SMRAM
area is from 38000h–3FFFFh. The default value for SM-
BASE is 30000h.
As illustrated in Figure 31, the starting address of the
jump vector is calculated by:
SMBASE + 8000h
The starting address for the SMRAM state save area is
calculated by:
SMBASE + [8000h + 7FFFh]
When this feature is enabled, the SMRAM register map
is addressed according to the above formula.
31
31
AMD
X
Figure 30. SMM Base Slot Offset
86 CPU family provides a new control regis-
0
0
SMM Base
Register Offset 7EF8h
Am5
X
PRELIMINARY
86 Microprocessor
To change the SMRAM base address and SMI jump
vector location, SMI handler modifies the SMBASE slot.
Upon executing an RSM instruction, the processor
reads the SMBASE slot and stores it internally. Upon
recognition of the next SMI request, the processor uses
the new SMBASE slot for the SMRAM dump and SMI
jump vector. If the modified SMBASE slot does not con-
tain a 32-Kbyte aligned value, the RSM microcode caus-
es the CPU to enter the shutdown state.
7.8
7.8.1 SMRAM Interface
The hardware designed to control the SMRAM space
must follow these guidelines:
Initialize SMRAM space during system boot up. Ini-
tialization must occur before the first SMI occurs.
Initialization of SMRAM space must include installa-
tion of an SMI handler and may include installation
of related data structures necessary for particular
SMM applications. The memory controller interfac-
ing SMRAM should provide a means for the initial-
ization code to open the SMRAM space manually.
The memory controller must decode a minimum ini-
tial SMRAM address space of 38000h–3FFFFh.
Alternate bus masters (such as DMA controllers)
must not be able to access SMRAM space. The sys-
tem should allow only the CPU, either through SMI
or during initialization, to access SMRAM.
To implement a 0-V suspend function, the system
must have access to all normal system memory from
within an SMI handler routine. If the SMRAM over-
lays normal system memory (see Figure 32), there
must be a method to access overlaid system mem-
ory independently.
SMBASE + 8000h
SMBASE + 8000h
SMM System Design Considerations
SMBASE
+ 7FFFh
Figure 31. SRAM Usage
Start of State Save
SMI Handler Entry Point
SMRAM