AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 17

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

for at least two clocks to guarantee recognition. When
the CPU recognizes SMI, it enters SMM before execut-
ing the next instruction and saves internal registers in
SMM space.
SMIACT
SMM Interrupt Active (Active Low; Output)
SMIACT goes Low in response to SMI. It indicates that
the processor is operating under SMM control. SMIACT
remains Low until the processor receives a RESET sig-
nal or executes the Resume Instruction (RSM) to leave
SMM. This signal is always driven. It does not float dur-
ing bus HOLD or BOFF.
Note: Do not use SRESET to exit from SMM. The sys-
tem should block SRESET during SMM.
SRESET
Soft Reset (Active High; Input)
The CPU samples SRESET on every rising clock edge.
If SRESET is sampled active, the SRESET sequence
begins on the next instruction boundary. SRESET
resets the processor, but, unlike RESET, does not cause
it to sample UP or WB/WT, or affect the FPU, cache, CD
and NW bits in CR0, and SMBASE. SRESET is asyn-
chronous and must meet the same timing as RESET.
The SRESET input has an internal pull-down resistor.
STPCLK
Stop Clock (Active Low; Input)
A Low input signal indicates a request has been made
to turn off the CLK input. When the CPU recognizes a
STPCLK, the processor:
STPCLK is active Low and has an internal pull-up re-
sistor. STPCLK is asynchronous, but it must meet setup
and hold times t
specific clock. STPCLK must remain active until the Stop
Clock special bus cycle is issued and the system returns
either RDY or BRDY.
TCK
Test Clock (Input)
Test Clock provides the clocking function for the JTAG
boundary scan feature. TCK clocks state information
and data into the component on the rising edge of TCK
on TMS and TDI, respectively. Data is clocked out of
the component on the falling edge of TCK on TDO.
TDI
Test Data Input (Input)
TDI is the serial input that shifts JTAG instructions and
data into the tested component. TDI is sampled on the
Stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt)
Empties all internal pipelines and write buffers
Generates a Stop Grant acknowledge bus cycle
20
and t
21
to ensure recognition in any
Am5
X
PRELIMINARY
86 Microprocessor
rising edge of TCK during the SHIFT-IR and the
SHIFT-DR TAP (Test Access Port) controller states.
During all other TAP controller states, TDI is ignored.
TDI uses an internal weak pull-up.
TDO
Test Data Output (Active High; Output)
TDO is the serial output that shifts JTAG instructions
and data out of the component. TDO is driven on the
falling edge of TCK during the SHIFT-IR and SHIFT-DR
TAP controller states. Otherwise, TDO is tri-stated.
TMS
Test Mode Select (Active High; Input)
TMS is decoded by the JTAG TAP to select the operation
of the test logic. TMS is sampled on the rising edge of
TCK. To guarantee deterministic behavior of the TAP
controller, the TMS pin has an internal pull-up resistor.
UP
Write/Read (Input)
The processor samples the Upgrade Present (UP) pin
in the clock before the falling edge of RESET. If it is Low,
the processor tri-states its outputs immediately. UP
must remain asserted to keep the processor inactive.
The pin uses an internal pull-up resistor.
VOLDET—(168-pin PGA package only)
Voltage Detect (Output)
VOLDET provides an external signal to allow the system
to determine the CPU input power level (3 V or 5 V). For
Am5
WB/WT
Write-Back/Write-Through (Input)
If the processor samples WB/WT High at RESET, the
processor is configured in Write-back mode and all sub-
sequent cache line fills sample WB/WT on the same
clock edge in which it finds either RDY or the first BRDY
of a burst transfer to determine if the cache line is des-
ignated as Write-back mode or Write-through. If the sig-
nal is Low on the first BRDY or RDY, the cache line is
write-through. If the signal is High, the cache line is write-
back. If WB/WT is sampled Low at RESET, all cache
line fills are write-through. WB/WT has an internal weak
pull-down.
W/R
Write/Read (Output)
A High output indicates a write cycle. A Low output in-
dicates a read cycle.
Note: The Am5
V
processors. The corresponding pin on the Am5
croprocessor is an Internal No Connect (INC).
CC5
X
86 processors, the pin ties internally to V
pin used by some 3-V, clock-tripled, 486-based
X
86 microprocessor does not use the
AMD
SS
X
86 mi-
.
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