AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 36

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

36
4.10.3 PLOCK Operation in Write-Through Mode
As described in Section 3, PLOCK is only used in Write-
through mode; the signal is driven inactive in Write-back
mode. In Write-through mode, the processor drives
PLOCK Low to indicate that the current bus transaction
requires more than one bus cycle. The CPU continues
to drive the signal Low until the transaction is completed,
whether or not RDY or BRDY is returned. Refer to the
pin description for additional information.
5
5.1
The Am5
phased-lock loop (PLL) to generate the two internal
clock phases: phase one and phase two. The rising edge
of CLK corresponds to the start of phase one (ph1). All
external timing parameters are specified relative to the
rising edge of CLK.
5.2
The Am5
nism, STPCLK, that allows system hardware to control
the power consumption of the CPU by stopping the in-
ternal clock to the CPU core in a sequenced manner.
The first low-power state is called the Stop Grant state.
If the CLK input is completely stopped, the CPU enters
into the Stop Clock state (the lowest power state). When
the CPU recognizes a STPCLK interrupt, the processor:
At this point the CPU is in the Stop Grant state.
The CPU cannot respond to a STPCLK request from an
HLDA state because it cannot empty the write buffers
and, therefore, cannot generate a Stop Grant cycle. The
rising edge of STPCLK signals the CPU to return to
program execution at the instruction following the inter-
rupted instruction. Unlike the normal interrupts (INTR
and NMI), STPCLK does not initiate interrupt acknowl-
edge cycles or interrupt table reads.
5.2.1 External Interrupts in Order of Priority
In Write-through mode, the priority order of external in-
terrupts is:
1. RESET/SRESET
2. FLUSH
3. SMI
4. NMI
5. INTR
6. STPCLK
Stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt)
Waits for completion of cache flush
Stops the pre-fetch unit
Empties all internal pipelines and write buffers
Generates a Stop Grant bus cycle
Stops the internal clock
AMD
CLOCK CONTROL
Clock Generation
Stop Clock
X
X
86 CPU is driven by a 1x clock that relies on
86 CPU also provides an interrupt mecha-
Am5
X
PRELIMINARY
86 Microprocessor
In Write-back mode, the priority order of external inter-
rupts is:
1. RESET
2. FLUSH
3. SRESET
4. SMI
5. NMI
6. INTR
7. STPCLK
STPCLK is active Low and has an internal pull-up re-
sistor. STPCLK is asynchronous, but setup and hold
times must be met to ensure recognition in any specific
clock. STPCLK must remain active until the Stop Grant
special bus cycle is asserted and the system responds
with either RDY or BRDY. When the CPU enters the
Stop Grant state, the internal pull-up resistor is disabled,
reducing the CPU power consumption. The STPCLK
input must be driven High (not floated) to exit the Stop
Grant state. STPCLK must be deasserted for a minimum
of five clocks after RDY or BRDY is returned active for
the Stop Grant bus cycle before being asserted again.
There are two regions for the Low-power mode supply
current:
1. Low Power: Stop Grant state (fast wake-up, frequency-
2. Lowest Power: Stop Clock state (slow wake-up, volt-
5.3
The processor drives a special Stop Grant bus cycle to
the bus after recognizing the STPCLK interrupt. This
bus cycle is the same as the HALT cycle used by a
standard Am486 microprocessor, with the exception
that the Stop Grant bus cycle drives the value 0000
0010h on the address pins.
The system hardware must acknowledge this cycle by
returning RDY or BRDY, or the processor will not enter
the Stop Grant state (see Figure 19). The latency be-
tween a STPCLK request and the Stop Grant bus cycle
depends on the current instruction, the amount of data
in the CPU write buffers, and the system memory per-
formance.
M/lO = 0
D/C = 0
W/R =1
Address Bus = 0000 0010h (A
BE3–BE0 = 1011
Data bus = undefined
and voltage-dependent)
age-dependent)
Stop Grant Bus Cycle
4
= 1)