AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 14

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

14
BS8/BS16
Bus Size 8 (Active Low; Input)/
Bus Size 16 (Active Low; Input)
The BS8 and BS16 signals allow the processor to op-
erate with 8-bit and 16-bit I/O devices by running multiple
bus cycles to respond to data requests: four for 8-bit
devices, and two for 16-bit devices. The bus sizing pins
are sampled every clock. The microprocessor samples
the pins every clock before RDY to determine the ap-
propriate bus size for the requesting device. The signals
are active Low input with internal pull-up resistors, and
must satisfy setup and hold times t
operation. Bus sizing is not permitted during copy-back
or write-back operation. BS8 and BS16 are ignored dur-
ing copy-back or write-back cycles.
CACHE
Internal Cacheability (Active Low; Output)
In Write-through mode, this signal always floats. In
Write-back mode for processor-initiated cycles, a Low
output on this pin indicates that the current read cycle
is cacheable, or that the current cycle is a burst write-
back or copy-back cycle. If the CACHE signal is driven
High during a read, the processor will not cache the data
even if the KEN pin signal is asserted. If the processor
determines that the data is cacheable, CACHE goes
active when ADS is asserted and remains in that state
until the next RDY or BRDY is asserted. CACHE floats
in response to a BOFF or HOLD request.
CLK
Clock (Input)
The CLK input provides the basic microprocessor timing
signal. The CLKMUL input selects the multiplier value
used to generate the internal operating frequency for
the Am5
parameters are specified with respect to the rising edge
of CLK. The clock signal passes through an internal
Phase-Lock Loop (PLL).
CLKMUL
Clock Multiplier (Input)
The microprocessor samples the CLKMUL input signal
at RESET to determine the design operating frequency.
An internal pull-up resistor connects to V
lects Clock-tripled mode if the input is High or left float-
ing. For Clock-quadrupled mode, the input must be
pulled Low. For 133-MHz processors, this input must
always be connected to V
D31
Data Lines (Inputs/Outputs)
Lines D31–D0 define the data bus. The signals must
meet setup and hold times t
operations. These pins are driven during the second
and subsequent clocks of write cycles.
–
AMD
D0
X
86 microprocessor family. All external timing
SS
to ensure correct operation.
22
and t
14
23
and t
for proper read
CC
15
, which se-
Am5
for correct
X
PRELIMINARY
86 Microprocessor
D/C
Data/Control (Output)
This bus cycle definition pin distinguishes memory and
I/O data cycles from control cycles. The control cycles
are:
DP3
Data Parity (Inputs/Outputs)
Data parity is generated on all write data cycles with the
same timing as the data driven by the microprocessor.
Even parity information must be driven back into the
microprocessor on the data parity pins with the same
timing as read information to ensure that the processor
uses the correct parity check. The signals read on these
pins do not affect program execution. Input signals must
meet setup and hold times t
be connected to V
tems not using parity. DP3–DP0 are active High and are
driven during the second and subsequent clocks of write
cycles.
EADS
External Address Strobe (Active Low; Input)
This signal indicates that a valid external address has
been driven on the address pins A31–A4 of the micro-
processor to be used for a cache snoop. This signal is
recognized while the processor is in hold (HLDA is driv-
en active), while forced off the bus with the BOFF input,
or while AHOLD is asserted. The microprocessor ig-
nores EADS at all other times. EADS is not recognized
if HITM is active, nor during the clock after ADS, nor
during the clock after a valid assertion of EADS. Snoops
to the on-chip cache must be completed before another
snoop cycle is initiated. Table 2 describes EADS when
first sampled. EADS can be asserted every other clock
cycle as long as the hold remains active and HITM re-
mains inactive. INV is sampled in the same clock period
that EADS is asserted. EADS has an internal weak pull-
up.
Note:
The triggering signal (AHOLD, HOLD, or BOFF) must remain
active for at least 1 clock after EADS to ensure proper oper-
ation.
Interrupt Acknowledge
Halt/Special Cycle
Code Read (instruction fetching)
Trigger
AHOLD
HOLD
BOFF
–
DP0
Table 2. EADS Sample Time
Second clock after AHOLD asserted
First clock after HLDA asserted
Second clock after BOFF asserted
CC
through a pull-up resistor in sys-
EADS First Sampled
22
and t
23
. DP3–DP0 should