AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 32

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

32
4.8.7.2
The use of BOFF to perform snooping of the on-chip
cache is used in systems where more than one cache-
able bus master resides on the microprocessor bus. The
BOFF signal forces the microprocessor to relinquish the
bus in the following clock cycle, regardless of the type
of bus cycle it was performing at the time. Consequently,
the use of BOFF as a bus arbitrator should be imple-
mented with care to avoid system problems.
4.8.8 BOFF Design Considerations
The use of BOFF as a bus arbitration control mechanism
is immediate. BOFF forces the microprocessor to abort
an access in the following clock cycle after it is asserted.
The following design issues must be considered.
4.8.8.1
The microprocessor aborts a cache line fill during a burst
read if BOFF is asserted during the access. Upon re-
gaining the bus, the read access commences where it
left off when BOFF was recognized. External buffers
should take this cycle continuation into consideration if
BOFF is allowed to abort burst read cycles.
4.8.8.2
Similar to the burst read, the burst write also can be
aborted at any time with the BOFF signal. Upon regain-
ing access to the bus, the write continues from where it
was aborted. External buffers and control logic should
take into consideration the necessary control, if any, for
burst write continuations.
4.8.8.3
Locked bus cycles occur in various forms. Locked ac-
cesses occur during read-modify-write operations, in-
terrupt acknowledges, and page table updates.
Although asserting BOFF during a locked cycle is per-
mitted, extreme care should be taken to ensure data
coherency for semaphore updates and proper data or-
dering.
4.8.9 BOFF During Write-Back
If BOFF is asserted during a write-back, the processor
performing the write-back goes off the bus in the next
clock cycle. If BOFF is released, the processor restarts
that write-back access from the point at which it was
aborted. The behavior is identical to the normal BOFF
case that includes the abort and restart behavior.
AMD
BOFF Write-Back Arbitration
Implementation
Cache Line Fills
Cache Line Copy-Backs
Locked Accesses
Am5
X
PRELIMINARY
86 Microprocessor
4.8.10 Snooping Characteristics During a Cache
The microprocessor takes responsibility for responding
to snoop cycles for a cache line only during the time that
the line is actually in the cache or in a copy-back buffer.
There are times during the cache line fill cycle and during
the cache replacement cycle when the line is “in transit”
and snooping responsibility must be taken by other sys-
tem components.
The following cases apply if snooping is invoked via
AHOLD, and neither HOLD nor BOFF is asserted.
4.8.11 Snooping Characteristics During a
If a copy-back is occurring because of a cache line re-
placement, the address being replaced can be matched
by a snoop until assertion of the last BRDY of the copy-
back. This is when the modified line resides in the copy-
back buffer. An EADS as late as two clocks before the
last BRDY can cause HITM to be asserted.
Figure 15 illustrates the microprocessor relinquishing
responsibility of recognizing snoops for a line that is
copied back. It shows the latest EADS assertion that
can cause HITM assertion. HITM remains active for only
one clock period in that example. HITM remains active
through the last BRDY of the corresponding write-back;
in that case, the write-back has already completed. This
is the latest point where snooping can start, because
two clock cycles later, the final BRDY of the write-back
is applied.
If a snoop cycle hits the copy-back address after the first
BRDY of the copy-back and ADS has been issued, the
microprocessor asserts HITM. Keep in mind that the
write-back was initiated due to a read miss and not due
to a snoop to a modified line. In the second case, no
snooping is recognized if a modified line is detected.
System designers should consider the possibility
that a snooping cycle may arrive at the same time
as a cache line fill or replacement for the same ad-
dress. If a snooping cycle arrives at the same time
as a cache line fill with the same address, the CPU
uses the cache line fill, but does not place it in the
cache.
If a snooping cycle occurs at the same time as a
cache line fill with a different address, the cache line
fill is placed into the cache unless EADS is recog-
nized before the first BRDY but after ADS is assert-
ed, or EADS is recognized on the last BRDY of the
cache line fill. In these cases, the line is not placed
into the cache.
Line Fill
Copy-Back