AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 35

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

CACHE is asserted for cacheable reads, cacheable
code fetches, and write-backs/copy-backs. CACHE is
deasserted for non-cacheable reads, translation looka-
side buffer (TLB) replacements, locked cycles (except
for write-back cycles generated by an external snoop
operation that interrupts a locked read/modify/write se-
quence), I/O cycles, special cycles, and write-throughs.
CACHE is driven to its valid level in the same clock as
the assertion of ADS and remains valid until the next
RDY or BRDY assertion. The CACHE output pin floats
one clock after BOFF is asserted. Additionally, the signal
floats when HLDA is asserted.
The following steps describe the burst write sequence:
1. The access is started by asserting: ADS = 0, M/IO
2. In the second clock cycle, BLAST is 1 to indicate
3. The burst write access is finished when BLAST is
When the RDY signal is returned instead of the BRDY
signal, the Am5
and proceeds with the standard non-burst cycle.
4.10.1 Locked Accesses
Locked accesses of an Am5
for read-modify-write operations and interrupt acknowl-
edge cycles. The timing is identical to the DX micropro-
cessor, although the state transitions differ from the
standard DX microprocessor. Unlike processor-initiated
accesses, state transitions for locked accesses are seen
by all processors in the system. Any locked read or write
CACHE
ADS
BLAST
BRDY
BOFF
Data
from CPU
CLK
ADR
M/IO
W/R
= 1, W/R = 1, CACHE = 0. The address offset always
is 0, so the burst write always starts on a cache line
boundary. CACHE transitions High (inactive) after
the first BRDY.
that the burst is not finished.
0 and BRDY is 0.
X
86 microprocessor halts the burst cycle
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86 microprocessor occur
Figure 18. Burst Write with BOFF Assertion
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PRELIMINARY
86 Microprocessor
generates an external bus cycle, regardless of cache
hit or miss. During locked cycles, the processor does
not recognize a HOLD request, but it does recognize
BOFF and AHOLD requests.
Locked read operations always read data from the ex-
ternal memory, regardless of whether the data is in the
cache. In the event that the data is in the cache and
unmodified, the cache line is invalidated and an external
read operation is performed. The data from the external
memory is used instead of the data in the cache, thus
ensuring that the locked read is seen by all other bus
masters. If a locked read occurs, the data is in the cache,
and it is modified. The microprocessor first copies back
the data to external memory, invalidates the cache line,
and then performs a read operation to the same location,
thus ensuring that the locked read is seen by all other
bus masters. At no time is the data in the cache used
directly by the microprocessor or a locked read opera-
tion before reading the data from external memory.
Since locked cycles always begin with a locked read
access, and locked read cycles always invalidate a
cache line, a locked write cycle to a valid cache line,
either modified or unmodified, does not occur.
4.10.2 Serialization
Locked accesses are totally serialized:
All reads and writes in the write buffer that precede
the locked access are issued on the bus before the
first locked access is executed.
No read or write after the last locked access is issued
internally or on the bus until the final RDY or BRDY
for all locked accesses.
It is possible to get a locked read, write-back, locked
write cycle.
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