AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 22

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

22
4.8.2.2
The HOLD/HLDA bus arbitration scheme is used prima-
rily in systems where all memory transfers are seen by
the microprocessor. The HOLD/HLDA bus arbitration
scheme permits simple write-back cache design while
maintaining a relatively high performing system. Figure
3 shows a typical system block diagram for HOLD/HLDA
bus arbitration.
Note: To maintain proper system timing, the HOLD
signal must remain active for one clock cycle after HITM
transitions active. Deassertion of HOLD in the same
clock cycle as HITM assertion may lead to unpredictable
processor behavior.
4.8.2.2.1 Processor-Induced Bus Cycles
In the following scenarios, read accesses are assumed
to be cache line fills. The cases also assume that the
core system logic does not return BRDY or RDY until
HITM is sampled. The addition of wait states follows the
standard 486 bus protocol. For demonstration purpos-
es, only the zero wait state approach is shown. Table 6
explains the key to switching waveforms.
Address Bus
Data Bus
AMD
Figure 3. Typical System Block Diagram
HOLD Bus Arbitration Implementation
L2 Cache
for HOLD/HLDA Bus Arbitration
DRAM
CPU
Peripheral
Peripheral
Local Bus
Interface
I/O Bus
Slow
Address Bus
Data Bus
Am5
X
PRELIMINARY
86 Microprocessor
.
4.8.2.2.2 External Read
Scenario : The data resides in external memory (see
Figure 4).
Step 1 The processor starts the external read access
Step 2 WB/WT is sampled in the same cycle as BRDY.
Step 3 The processor completes its burst read and as-
4.8.2.2.3 External Write
Scenario: The data is written to the external memory
(see Figure 5).
Step 1 The processor starts the external write access
Step 2 The processor completes its write to the core
4.8.2.2.4 HOLD/HLDA External Access TIming
In systems with two or more bus masters, each bus
master is equipped with individual HOLD and HLDA con-
trol signals. These signals are then centralized to the
core system logic that controls individual bus masters,
depending on bus request signals and the HITM signal.
Waveform
Table 6. Key to Switching Waveforms
by asserting ADS = 0 and W/R = 0.
If WB/WT = 1, the data resides in a write-back
cacheable memory location.
serts BLAST.
by asserting ADS = 0 and W/R = 1.
system logic.
Inputs
Must be steady
May change from
H to L
May change from
L to H
Don’t care; any
change permitted
Does not apply
Outputs
Will be steady
Will change
from H to L
Will change
from L to H
Changing;
state unknown
Center line is
High-impedance
“Off” state