AMD-X5-133ADW AMD [Advanced Micro Devices], AMD-X5-133ADW Datasheet - Page 25

• Manufacturer Part Number: AMD-X5-133ADW
• Manufacturer: AMD [Advanced Micro Devices]

4.8.3 External Bus Master Snooping Actions
The following scenarios describe the snooping actions
of an external bus master.
4.8.3.1
Scenario : A snoop of the on-chip cache does not hit a
line, as shown in Figure 6.
Step 1 The microprocessor is placed in Snooping
Step 2 EADS and INV are applied to the microproces-
Step 3 Two clock cycles after EADS is asserted, HITM
4.8.3.2
Scenario : The snoop of the on-chip cache hits a line,
and the line is not modified (see Figure 7).
Step 1 The microprocessor is placed in Snooping
ADR
M/IO
CACHE
W/R
ADS
BLAST
BRDY
INV
EADS
HITM
CLK
HOLD
HLDA
Data
External
bus master’s
BOFF signal
Note:
The circled numbers in this figure represent the steps in section 4.8.4.
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
becomes valid. Because the addressed line is
not in the snooping cache, HITM is 1.
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
Snoop Miss
Snoop Hit to a Non-Modified Line
1
valid
floating/tri-stated
n
2
Figure 8. Snoop That Hits a Modified Line (Write-Back)
3
4
Am5
X
PRELIMINARY
86 Microprocessor
5
n
n
n+4
n+4
Step 2 EADS and INV are applied to the microproces-
Step 3 Two clock cycles after EADS is asserted, HITM
4.8.4 Write-Back Case
Scenario : Write-back accesses are always burst writes
with a length of four 32-bit words. For burst writes, the
burst always starts with the microprocessor line offset
at 0. HOLD must be deasserted before the write-back
can be performed (see Figure 8).
Step 1 HOLD places the microprocessor in Snooping
Step 2 EADS and INV are asserted. If INV is 0, snoop-
n+8 n+12
n+8
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
becomes valid. In this case, HITM is 1.
mode. HLDA must be High for a minimum of
one clock cycle before EADS assertion. In the
fastest case, this means that HOLD asserts one
clock cycle before the HLDA response.
ing is caused by a read access. If INV is 1,
snooping is caused by a write access. EADS is
not sampled again until after the modified line
is written back to memory. It is detected again
as early as in Step 11.
n+1
6
valid
7
8
9
11
floating/tri-stated
10
AMD
n
25