AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 30
AMD-K6-2E/400AFR
Manufacturer Part Number
AMD-K6-2E/400AFR
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AMD-K6-2E400AFR.pdf
(332 pages)
- Current page: 30 of 332
- Download datasheet (6Mb)
AMD-K6™-2E Processor Data Sheet
2.2
Cache
Figure 2. Cache Sector Organization
Prefetching
12
Tag Address
Cache, Instruction Prefetch, and Predecode Bits
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
The writeback level-one cache on the AMD-K6-2E processor is
organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are prefetched from main memory
using an efficient pipelined burst transaction.
As the instruction cache is filled, each instruction byte is
analyzed for instruction boundaries using predecoding logic.
Predecoding annotates each instruction byte with information
(5 bits per byte) that later enables the decoders to efficiently
decode multiple instructions simultaneously.
The processor cache design takes advantage of a sectored
organization (see Figure 2). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate pairs of MESI
(Modified, Exclusive, Shared, Invalid) bits that track the state
of each cache line.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
The AMD-K6-2E processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
Tag-miss cache fill—The miss is due to a tag mismatch, in
which case the required cache line is filled from external
memory, and the cache line within the sector that was not
required is marked as invalid.
Tag-hit cache fill—The address matches the tag, but the
requested cache line is marked as invalid. The required
cache line is filled from external memory, and the cache line
within the sector that is not required remains in the same
cache state.
Preliminary Information
Internal Architecture
22529B/0—January 2000
Chapter 2
Related parts for AMD-K6-2E/400AFR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
AMD-K6 Processor
Manufacturer:
AMD [Advanced Micro Devices]
Datasheet:
Part Number:
Description:
Manufacturer:
AMD (ADVANCED MICRO DEVICES)
Datasheet:
Part Number:
Description:
AMD CPUs, K6-2 550 MHz, Includes: Cooling Fan
Manufacturer:
AMD (ADVANCED MICRO DEVICES)
Part Number:
Description:
AMD-751ACAMD-751-TM System Controller Revision Guide
Manufacturer:
Advanced Micro Devices
Datasheet:
Part Number:
Description:
AMD-751AMD-751-TM System Controller Revision Guide
Manufacturer:
Advanced Micro Devices
Datasheet:
Part Number:
Description:
AMD-X5-133SFZAm5X86? Microprocessor Family
Manufacturer:
Advanced Micro Devices
Datasheet:
Part Number:
Description:
Hyper Transport PCI-X Tunnel
Manufacturer:
Advanced Micro Devices
Datasheet:
Part Number:
Description:
HyperTransport I/O Hub
Manufacturer:
Advanced Micro Devices
Datasheet:
Part Number:
Description:
System Controller
Manufacturer:
Advanced Micro Devices
Datasheet:
Part Number:
Description:
Manufacturer:
AMD (ADVANCED MICRO DEVICES)
Datasheet:
Part Number:
Description:
Peripheral Bus Controller
Manufacturer:
AMD [Advanced Micro Devices]
Datasheet: