AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 203

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
8
Figure 74. Cache Organization
Chapter 8
Interface Unit
System Bus
Cache Organization
RAM
Tag
RAM
The following sections describe the basic architecture and
resources of the AMD-K6-2E processor internal caches.
The performance of the AMD-K6-2E processor is enhanced by a
writeback level-one (L1) cache. The cache is organized as a
separate 32-Kbyte instruction cache and a 32-Kbyte data cache,
each with two-way set associativity (See Figure 74). The cache
line size is 32 bytes, and lines are prefetched from external
memory using an efficient, pipelined burst transaction.
As the instruction cache is filled, each instruction byte is
analyzed for instruction boundaries using predecode logic.
Predecoding annotates each instruction byte with information
that later enables the decoders to efficiently decode multiple
instructions simultaneously. Translation lookaside buffers
(TLB) are also used to translate linear addresses to physical
addresses. The instruction cache is associated with a 64-entry
TLB, while the data cache is associated with a 128-entry TLB.
Tag
Way 0
Way 0
Predecode Instruction Cache
32-Kbyte Instruction Cache
Cache Organization
32-Kbyte Data Cache
128-Entry TLB
64-Entry TLB
MESI
State
Bits
Bit
RAM
RAM
Tag
Tag
Way 1
Way 1
MESI
Bits
AMD-K6™-2E Processor Data Sheet
State
Bit
Processor
Core
185