AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 211

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
Write to a Cacheable
Page
Write to a Sector
Write Allocate Limit
Chapter 8
negated, the processor does not perform an allocation. In this
case, the pending write cycle is executed as a single write cycle
on the system bus.
During write allocates, a 32-byte burst read cycle is executed in
place of a non-burst write cycle. While the burst read cycle
generally takes longer to execute than the write cycle,
performance gains are realized on subsequent write cycle hits
to the write-allocated cache line. Due to the nature of software,
memory accesses tend to occur in proximity of each other
(principle of locality). The likelihood of additional write hits to
the write-allocated cache line is high.
The following is a description of three mechanisms by which the
AMD-K6-2E processor performs write allocations. A write
al lo c at e is p e r fo rm e d wh en a ny o n e o r m o re of t h e se
mechanisms indicates that a pending write is to a cacheable
area of memory.
Every time the processor performs a cache line fill, the address
of the page in which the cache line resides is saved in the
Cacheability Control Register (CCR). The page address of
subsequent write cycles is compared with the page address
stored in the CCR. If the two addresses are equal, then the
processor performs a write allocate because the page has
already been determined to be cacheable.
When the processor performs a cache line fill from a different
page than the address saved in the CCR, the CCR is updated
with the new page address.
If the address of a pending write cycle matches the tag address
of a valid cache sector, but the addressed cache line within the
sector is marked invalid (a sector hit but a cache line miss),
then the processor performs a write allocate. The pending write
cycle is determined to be cacheable because the sector hit
indicates the presence of at least one valid cache line in the
sector. The two cache lines within a sector are guaranteed by
design to be within the same page.
The AMD-K6-2E processor uses two mechanisms that are
programmable within the Write Handling Control register
(WHCR) to enable write allocations for write cycles that
address a definable or special 1-Mbyte memory area.
Cache Organization
AMD-K6™-2E Processor Data Sheet
193