AMD-K6-2E/400AFR AMD [Advanced Micro Devices], AMD-K6-2E/400AFR Datasheet - Page 237

• Manufacturer Part Number: AMD-K6-2E/400AFR
• Manufacturer: AMD [Advanced Micro Devices]

22529B/0—January 2000
11.2
Chapter 11
SMM State-Save Area
Table 40 shows the initial state of registers when entering SMM.
Table 40. Initial State of Registers in System Management Mode (SMM)
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 41. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 41 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 41. SMM State-Save Area Map
Register
General-Purpose Registers
EFLAGs
CR0
DR7
GDTR, LDTR, IDTR, TSSR, DR6 Unmodified
EIP
CS
DS, ES, FS, GS, SS
System Management Mode (SMM)
Address Offset
FFDCh
FFECh
FFD8h
FFD4h
FFD0h
FFFCh
FFF8h
FFF4h
FFF0h
FFE8h
FFE4h
FFE0h
SMM Initial State
Unmodified
0000_0002h
PE, EM, TS, and PG are cleared (bits 0, 2, 3, and 31).
The other bits are unmodified.
0000_0400h
0000_8000h
0003_0000h
0000_0000h
AMD-K6™-2E Processor Data Sheet
Contents Saved
EFLAGS
CR0
CR3
EBP
EBX
EDX
ECX
EAX
ESP
EDI
EIP
ESI
219