MC68020 Motorola, MC68020 Datasheet - Page 86

• Manufacturer Part Number: MC68020
• Description: (MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
• Manufacturer: Motorola

State 4
State 5
5.3.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read, conditionally modifies the data in the
arithmetic logic unit, and may write the data out to memory. In the MC68020/EC020, this
operation is indivisible, providing semaphore capabilities for multiprocessor systems.
During the entire read-modify-write sequence, the MC68020/EC020 asserts RMC to
indicate that an indivisible operation is occurring. The MC68020/EC020 does not issue a
BG signal in response to a BR signal during this operation.
The TAS, CAS, and CAS2 instructions are the only MC68020/EC020 instructions that
utilize read-modify-write operations. Depending on the compare results of the CAS and
CAS2 instructions, the write cycle(s) may not occur.
Figure 5-29 is a flowchart of the read-modify-write cycle operation. Figure 5-30 is an
example timing diagram of a TAS instruction specified in terms of clock periods.
MOTOROLA
MC68020/EC020—The processor issues no new control signals during S4.
MC68020—The processor negates AS and DS during S5. It holds the address and data
MC68EC020—The processor negates AS and DS during S5. It holds the address and
valid during S5 to provide address hold time for memory systems. R/W , SIZ1, SIZ0,
FC2–FC0, and DBEN also remain valid throughout S5.
The external device must keep DSACK1/DSACK0 asserted until it detects the negation
of AS or DS (whichever it detects first). The device must negate DSACK1/DSACK0
within approximately one clock period after sensing the negation of A S or DS.
DSACK1/DSACK0 signals that remain asserted beyond this limit may be prematurely
detected for the next bus cycle.
data valid during S5 to provide address hold time for memory systems. R/W , SIZ1,
SIZ0, and FC2–FC0 also remain valid throughout S5.
The external device must keep DSACK1/DSACK0 asserted until it detects the negation
of AS or DS (whichever it detects first). The device must negate DSACK1/DSACK0
within approximately one clock period after sensing the negation of A S or DS.
DSACK1/DSACK0 signals that remain asserted beyond this limit may be prematurely
detected for the next bus cycle.
M68020 USER’S MANUAL
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