MC68020 Motorola, MC68020 Datasheet - Page 79

• Manufacturer Part Number: MC68020
• Description: (MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
• Manufacturer: Motorola

State 4
State 5
5-32
MC68020/EC020—At the end of state 4 (S4), the processor latches the incoming data.
MC68020—The processor negates AS, DS, and DBEN during state 5 (S5). It holds the
MC68EC020—The processor negates AS and DS during state S5. It holds the address
address valid during S5 to provide address hold time for memory systems. R/W, SIZ1–
SIZ0, and FC2–FC0 also remain valid throughout S5.
The external device keeps its data and DSACK1/DSACK0 signals asserted until it
detects the negation of AS or DS (whichever it detects first). The device must remove
its data and negate DSACK1/DSACK0 within approximately one clock period after
sensing the negation of AS or DS. DSACK1/DSACK0 signals that remain asserted
beyond this limit may be prematurely detected for the next bus cycle.
valid during S5 to provide address hold time for memory systems. R/W , SIZ1, SIZ0,
and FC2–FC0 also remain valid throughout S5.
The external device keeps its data and DSACK1/DSACK0 signals asserted until it
detects the negation of AS or DS (whichever it detects first). The device must remove
its data and negate DSACK1/DSACK0 within approximately one clock period after
sensing the negation of AS or DS. DSACK1/DSACK0 signals that remain asserted
beyond this limit may be prematurely detected for the next bus cycle.
M68020 USER’S MANUAL
MOTOROLA