MC68020 Motorola, MC68020 Datasheet - Page 204

• Manufacturer Part Number: MC68020
• Description: (MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
• Manufacturer: Motorola

7.5.1.1 COPROCESSOR-DETECTED PROTOCOL VIOLATIONS. Protocol violation
exceptions are communication failures between the main processor and coprocessor
across the M68000 coprocessor interface. Coprocessor-detected protocol violations occur
when the main processor accesses entries in the CIR set in an unexpected sequence.
The sequence of operations that the main processor performs for a given coprocessor
instruction or coprocessor response primitive has been described previously in this
section.
A coprocessor can detect protocol violations in various ways. According to the M68000
coprocessor interface protocol, the main processor always accesses the operation word,
operand, register select, instruction address, or operand address CIRs synchronously with
respect to the operation of the coprocessor. That is, the main processor accesses these
five registers in a certain sequence, and the coprocessor expects them to be accessed in
that sequence. As a minimum, all M68000 coprocessors should detect a protocol violation
if the main processor accesses any of these five registers when the coprocessor is
expecting an access to either the command or condition CIR. Likewise, if the coprocessor
is expecting an access to the command or condition CIR and the main processor
accesses one of these five registers, the coprocessor should detect and signal a protocol
violation.
According to the M68000 coprocessor interface protocol, the main processor can perform
a read of either the save CIR or response CIR or a write of either the restore CIR or
control CIR asynchronously with respect to the operation of the coprocessor. That is, an
access to one of these registers without the coprocessor explicitly expecting that access
at that point can be a valid access. Although the coprocessor can anticipate certain
accesses to the restore, response, and control CIRs, these registers can be accessed at
other times also.
The coprocessor cannot signal a protocol violation to the main processor during execution
of a cpSAVE or cpRESTORE instruction. If a coprocessor detects a protocol violation
during execution of the cpSAVE or cpRESTORE instruction, it should signal the exception
to the main processor when the next coprocessor instruction is initiated.
The main philosophy of the coprocessor-detected protocol violation is that the
coprocessor should always acknowledge an access to one of its interface registers. If the
coprocessor determines that the access is not valid, it should assert DSACK1 / DSACK0 to
the main processor and signal a protocol violation when the main processor next reads
the response CIR. If the coprocessor fails to assert DSACK1 / DSACK0 , the main
processor waits for the assertion of that signal (or some other bus termination signal)
indefinitely. The protocol previously described ensures that the coprocessor cannot halt
the main processor.
The coprocessor can signal a protocol violation to the main processor with the take
midinstruction exception primitive. To maintain consistency, the vector number should be
13, as it is for a protocol violation detected by the main processor. When the main
processor reads this primitive, it proceeds as described in 7.4.19 Take Midinstruction
Exception Primitive. If the exception handler does not modify the stack frame, the
MC68020/EC020 returns from the exception handler and reads the response CIR.
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M68020 USER’S MANUAL
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