MC68020 Motorola, MC68020 Datasheet - Page 211

• Manufacturer Part Number: MC68020
• Description: (MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
• Manufacturer: Motorola

The MC68020/EC020 also services interrupts if it reads the not-ready format word from
the save CIR during a cpSAVE instruction. The MC68020/EC020 uses the normal four-
word preinstruction stack frame (see Figure 7-41) when it services interrupts after reading
the not-ready format word. Thus, the processor can service any pending interrupts and
execute an RTE to return and reinitiate the cpSAVE instruction by reading the save CIR.
7.5.2.7 FORMAT ERRORS. The MC68020/EC020 can detect a format error while
executing a cpSAVE or cpRESTORE instruction if the length field of a valid format word is
not a multiple of four bytes. If the MC68020/EC020 reads a format word with an invalid
length field from the save CIR during the cpSAVE instruction, it aborts the coprocessor
instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR) and
initiates format error exception processing. If the MC68020/EC020 reads a format word
with an invalid length field from the effective address specified in the cpRESTORE
instruction, the MC68020/EC020 writes that format word to the restore CIR and then reads
the coprocessor response from the restore CIR. The MC68020/EC020 then aborts the
cpRESTORE instruction by writing an abort mask to the control CIR (refer to 7.3.2
Control CIR) and initiates format error exception processing.
The MC68020/EC020 uses the four-word preinstruction stack frame (see Figure 7-41) and
the format error vector number 14 when it initiates format error exception processing.
Thus, if the exception handler does not modify the stack frame, the main processor, after it
executes an RTE to return from the handler, attempts to restart the instruction during
which the exception occurred.
7.5.2.8 ADDRESS AND BUS ERRORS. Coprocessor-instruction-related bus faults can
occur during main processor bus cycles to CPU space to communicate with a coprocessor
or during memory cycles run as part of the coprocessor instruction execution. If a bus
error occurs during the CIR access that is used to initiate a coprocessor instruction, the
main processor assumes that the coprocessor is not present and takes an F-line emulator
exception as described in 7.5.2.2 F-Line Emulator Exceptions. That is, the processor
takes an F-line emulator exception when a bus error occurs during the initial access to a
CIR by a coprocessor instruction. If a bus error occurs on any other coprocessor access
or on a memory access made during the execution of a coprocessor instruction, the main
processor performs bus error exception processing as described in Section 6 Exception
Processing. After the exception handler has corrected the cause of the bus error, the
main processor can return to the point in the coprocessor instruction at which the fault
occurred.
An address error occurs if the MC68020/EC020 attempts to prefetch an instruction from
an odd address. This can occur if the calculated destination address of a cpBcc or cpDBcc
instruction is odd or if an odd value is transferred to the scanPC with the transfer status
register and the scanPC response primitive. If an address error occurs, the
MC68020/EC020 performs exception processing for a bus fault as described in Section 6
Exception Processing.
7-58
M68020 USER’S MANUAL
MOTOROLA