MC68020 Motorola, MC68020 Datasheet - Page 111

• Manufacturer Part Number: MC68020
• Description: (MC68020 / MC68EC020) MICROPROCESSORS USERS MANUAL
• Manufacturer: Motorola

The timing diagram (see Figure 5-43) shows that BR is negated at the time that BGACK is
asserted. This type of operation applies to a system consisting of the processor and one
device capable of bus mastership. In a system having a number of devices capable of bus
mastership, the BR line from each device can be wire-ORed to the processor. In such a
system, more than one bus request can be asserted simultaneously.
The timing diagram in Figure 5-43 shows that BG is negated a few clock cycles after the
transition of BGACK. However, if bus requests are still pending after the negation of BG,
the processor asserts another BG within a few clock cycles after it was negated. This
additional assertion of BG allows external arbitration circuitry to select the next bus master
before the current bus master has finished with the bus. The following paragraphs provide
additional information about the three steps in the arbitration process.
Bus arbitration requests are recognized during normal processing, RESET assertion,
HALT assertion, and when the processor has halted due to a double bus fault.
5-64
Figure 5-42. MC68020 Bus Arbitration Flowchart for Single Request
1) ASSERT BG
1) NEGATE BG AND WAIT FOR BGACK TO
BE NEGATED
RE-ARBITRATE OR RESUME
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
PROCESSOR OPERATION
PROCESSOR
M68020 USER’S MANUAL
1) ASSERT BR
1) PERFORM DATA TRANSFERS
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR
3) NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
1) NEGATE BGACK
NEXT BUS MASTER
(READ AND WRITE CYCLES)
CURRENT CYCLE TO COMPLETE
ACKNOWLEDGE BUS MASTERSHIP
OPERATE AS BUS MASTER
RELEASE BUS MASTERSHIP
REQUESTING DEVICE
REQUEST THE BUS
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