cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 89

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

CX25840/1/2/3 Data Sheet
3.8.5
3.8.6
102284B
8/3/05
IR Controls
IR Status and Interrupts
General control of the IR functions is programmable through the IR Control 1 (0x200)
and IR Control 2 (0x201) registers. Features which are controlled using these registers
include the following:
The user can either program the IR port’s six control registers, in any order, then write
to the transmit FIFO to start operation, or first place data in the transmit FIFO, while
the IR port is disabled, then configure the six control registers, programming this
register last to enable the IR port. When changing any configuration in these registers,
always disable the IR’s transmitter and receiver first, then reprogram the mode of
operation and enable the receiver and transmitter.
The IR Status (0x210) register contains six status bits, four that can interrupt the
microprocessor and two that can be polled. Bits 5, 4, 1, and 0 are set and cleared
automatically by hardware and signal when a hardware condition exists which must be
handled by software. Any one of these four status bits produces an interrupt when set
and its corresponding interrupt enable bit is set. Interrupt enable bits do not affect the
setting and clearing of status bits. The transmit and receive busy flags are also set and
cleared automatically by hardware, bits 2 and 3, but do not produce interrupts. They
are polled by software to query whether the IR port is currently transmitting and/or
receiving IR data. The Interrupt Enable Register (IR_IRQEN_REG) is programmed
to enable/disable the transmit and receive FIFO service requests to signal interrupts to
the interrupt controller. This register is read-only; writes have no effect.
The IR Interrupt Enable (0x214) register contains four bits which are used to mask or
enable individual interrupt requests. Refer to the above IR Status (0x210) register for
a description of each interrupt source. The interrupt enable bits do not effect the
setting and clearing of the interrupt status bits. Each enable bit is logically ANDed
with its corresponding status bit, and the resultant signals are all logically ORed to
produce a single interrupt request to the interrupt controller.
RX FIFO load on timer overflow
Loopback operation
Carrier polarity
FIFO service request levels
Enabling/disabling of both the IR port’s transmitter and receiver
Enabling/disabling of the RX and TX FIFOs
Selection of carrier modulation and demodulation
Control of which type of edge to start and stop the pulse timer for demodulated
receive data
Control of a window which is used to predict when the next receive carrier
transition is expected
Conexant
Detailed Functional Description
3-63