CN8478EPF Conexant Systems, Inc., CN8478EPF Datasheet

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CN8478EPF

Manufacturer Part Number
CN8478EPF
Description
Multichannel synchronous communications controller
Manufacturer
Conexant Systems, Inc.
Datasheet

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Advance Information
This document contains information on a product under development. The parametric information
contains target parameters that are subject to change.
CN8478/CN8474A/CN8472A/CN8471A
Multichannel Synchronous Communications Controller (MUSYCC™)
Product Description
The CN8478, CN8474A, CN8472A, and CN8471A are advanced Multichannel
Synchronous Communication Controllers (MUSYCCs) that format and deformat up
to 256 (CN8478), 128 (CN8474A), 64 (CN8472A), or 32 (CN8471A) HDLC
channels in a single CMOS integrated circuit. MUSYCC operates at Layer 2 of the
Open Systems Interconnection (OSI) protocol reference model. MUSYCC provides
a comprehensive, high-density solution for processing HDLC channels for
internetworking applications such as Frame Relay, ISDN D-channel signaling,
X.25, Signaling System 7 (SS7), DXI, ISUP, and LAN/WAN data transport. Under
minimal host supervision, MUSYCC manages a linked list of channel data buffers
in host memory by performing Direct Memory Access (DMA) of the HDLC
channels.
signals, and then transfers data across the popular 32-bit Peripheral Component
Interface (PCI) bus to system memory at a rate of up to 66 MHz. Each serial
interface can be operated at up to 8.192 MHz. Logical channels can be mapped as
any combination of DS0 time slots to support ISDN hyperchannels (Nx64 kbps) or
as any number of bits in a DS0 for subchanneling applications (Nx8 kbps).
MUSYCC also includes a 32-bit expansion port for bridging the PCI bus to local
microprocessors or peripherals. A JTAG port enables boundary-scan testing to
replace bed-of-nails board testing.
available under a no-fee license agreement from Conexant. The device drivers
include C source code and supporting software documents.
Functional Block Diagram
100660E
MUSYCC interfaces with eight independent serial data streams, such as T1/E1
Device drivers for Linux, VxWorks
Configuration
Configuration
Configuration
(Function 0)
(Function 1)
Registers
Interface
Interface
Device
Space
Space
Host
PCI
PCI
PCI
Note: Number of serial interfaces is device-dependent.
Tx/Rx-DMAC
Controller
DMA
®
Channel Group 0 – Serial Interface
Channel Group 1 – Serial Interface
Channel Group 2 – Serial Interface
Channel Group 3 – Serial Interface
Channel Group 4 – Serial Interface
Channel Group 5 – Serial Interface
Channel Group 6 – Serial Interface
Channel Group 7 – Serial Interface
Boundary Scan and Test Access
, and pSOS™ operating systems are
Expanion Bus Interface
Controller
Interrupt
Conexant
Tx/Rx-BLP
Processor
Bit-Level
Interface
Tx/Rx
Port
Distinguishing Features
• 256-, 128-, 64-, or 32-channel HDLC
• OSI Layer 2 protocol support
• General purpose HDLC (ISO 3309)
• 8, 4, 2, or 1 independent serial interfaces
• Configurable logical channels
• Per-channel protocol mode selection
• Per-channel DMA buffer management
• Per-channel message length check
• Direct PCI bus interface
• Local Expansion Bus interface (EBUS)
• Low power, 3.3/2.5 V CMOS operation
• JTAG boundary scan access port
• 208-pin PQFP/surface-mount package
• BGA
Applications
• ISDN basic-rate or primary-rate interfaces
• ISDN D-channel controller
• Routers
• Cellular base station switch controller
• CSU/DSU
• Protocol converter
• Packet data switch
• Frame relay switches/Frame Relay Access
• DXI network interface
• Distributed packet-based communications
• Access multiplexer/concentrator
controller
– X.25 (LAPB)
– Frame relay (LAPF/ANSI T1.618)
– ISDN D-channel (LAPD/Q.921)
– SS7 support
which support
– T1/E1 data streams
– DC to 8.192 Mbps TDM busses
– Standard DS0 (56, 64 kbps)
– Hyperchannel (Nx64)
– Subchannel (Nx8)
– 16-bit FCS mode
– 32-bit FCS mode
– SS7 mode (16-bit FCS)
– Transparent mode (unformatted data)
– Linked list data structures
– Variable size transmit/receive FIFO
– Select no length checking
– Select from two 12-bit registers to
– Maximum length 16,384 Bytes
– 32-bit, 66 or 33 MHz operation
– Bus master and slave operation
– PCI Version 2.1
– 32-bit multiplexed address/data bus
– Burst access up to 64 Bytes
Devices (FRAD)
system
compare message length

Related parts for CN8478EPF

CN8478EPF Summary of contents

Page 1

Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Product Description The CN8478, CN8474A, CN8472A, and CN8471A are advanced Multichannel Synchronous ...

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... Ordering Information Model Number Version CN8471AEPF 32-Channel CN8472AEPF 64-Channel CN8474AEPF 128-Channel CN8478EPF 256-Channel CN8471AEBG 32-Channel CN8472AEBG 64-Channel CN8474AEBG 128-Channel CN8478EBG 256-Channel © 2000, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only ...

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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.0 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Buffer Status Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 6.3.16 Channel Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 7.0 Electrical and Mechanical Specifications 7.1 Electrical and Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents viii CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Conexant 100660E ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) List of Figures Figure 1-1. System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 7-10. EBUS Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) List of Tables Table 1-1. CN8478 MQFP Pin List . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 5-12. Port Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 7-13. EBUS I/O Measure Conditions ...

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List of Tables xiv CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Conexant 100660E ...

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System Description The Conexant MUSYCC is a high-throughput communications controller for synchronous, link-layer applications that multiplexes and demultiplexes up to 256 data channels. Each channel can be configured to support HDLC, Transparent, or SS7 applications. MUSYCC operates at ...

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System Description MUSYCC also provides an on-device, 32-bit local expansion bus (EBUS) controller which allows a host processor to access local memory and physical interface devices directly through MUSYCC over the PCI using configurable memory mapping features. MUSYCC manages ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 1-2. Detailed System Block Diagram Host Interface Device PCLK Configuration Registers PRST* INTB* INTA* GNT* REQ* PCI SERR* Interface PERR* IDSEL* PCI FRAME* Configuration IRDY* Space [Function 0] TRDY* DEVSEL* PCI STOP* Configuration ...

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System Description Figure 1-3. MUSYCC Application Example—Frame Relay Switch PHY PHY PHY System Bus – PCM Highway Tx Clk, Data, Clk, Data, Sync Sync, OOF Port 0 Port 1 Port 2 Ch Grp 0 Ch Grp 2 Ch Grp ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 1.1 Pin Descriptions Figures 1-4 through 1-7 illustrate the pinouts for CN8478, CN8474A, CN8472A, and CN8471A. Signals marked with black are NCs. Tables 1-1 and PBGA packages, respectively. Table 1-3 signal definitions. Figure 1-4. ...

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System Description 1.1 Pin Descriptions Table 1-1. CN8478 MQFP Pin List Pin Pin Label Number 1 RSYNC[7] 2 RDAT[7] 3 ROOF[3] 4 RCLK[3] 5 RSYNC[3] 6 RDAT[3] 7 ROOF[6] 8 RCLK[6] 9 RSYNC[6] 10 RDAT[6] 11 ROOF[2] 12 RCLK[2] ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Pin Pin Label Number 106 AD[3] 107 AD[2] 108 AD[1] 109 AD[0] 110 VDDo 111 VSSo 112 TM[2] 113 TM[1] 114 TM[0] 115 TDAT[4] 116 TSYNC[4] 117 TCLK[4] 118 VDDi 119 VSS 120 TDAT[0] ...

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System Description 1.1 Pin Descriptions Figure 1-5. CN8474A MPQF Pinout Configuration ROOF[3] 3 RCLK[ RSYNC[3] 6 RDAT[ ROOF[ RCLK[2] VDDp 13 VSS 14 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 1-6. CN8472A MQFP Pinout Configuration VDDp 13 VSS 14 ...

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System Description 1.1 Pin Descriptions Figure 1-7. CN8471A MQFP Pinout Configuration VDDp 13 VSS 14 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 1-8. CN8478 PBGA Pinout Configuration (Top View VSSo ROOF[7] A RCLK[7] NC RSYNC[7] NC HLDA(BG*) B VSSo EBE[0]* ROOF[3] VSSo C RDAT[7] EBE[1]* RDAT[3] RCLK[3] ROOF[6] D RSYNC[3] VSSo ...

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System Description 1.1 Pin Descriptions Table 1-2. CN8478 PBGA Pin List Pin Pin Label Number A1 VSSo A2 RCLK[7] A3 ROOF[ EBE[2]* A6 HOLD(BR*) A7 ECLK A8 EAD[29] A9 EAD[27] A10 EAD[23] A11 EAD[20] A12 EAD[18] ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Pin Pin Label Number J2 RCLK[4] J3 RDAT[1] J4 ROOF[0] J7 VSS J8 VSS J9 VSS J10 VSS J13 TCLK[1] J14 TDAT[1] J15 TSYNC[1] J16 TDAT[6] K1 RCLK[0] K2 RDAT[4] K3 RSYNC[4] K4 TRST* ...

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System Description 1.1 Pin Descriptions Figure 1-9. CN8474A PBGA Pinout Configuration (Top View VSSo NC EBE[2 HLDA(BG*) B VSSo EBE[0]* ROOF[3] VSSo EBE[3 EBE[1]* RDAT[3] RCLK[3] D RSYNC[3] ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 1-10. CN8472A PBGA Pinout Configuration (Top View VSSo NC EBE[2 HLDA(BG)* B VSSo EBE[0]* NC VSSo EBE[3 EBE[1 ...

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System Description 1.1 Pin Descriptions Figure 1-11. CN8471A PBGA Pinout Configuration (Top View VSSo NC EBE[2 HLDA(BG*) B VSSo EBE[0]* NC VSSo EBE[3 EBE[1 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 1-12. CN8478 Logic Diagram 198 Bus Grant Acknowledge I/O BGACK* 197 Hold Acknowledge I HLDA (BG*) 196 Hold Request O HOLD (BR*) 195 Expansion Bus Interrupt I EINT* 194 Address Latch Enable O ...

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System Description 1.1 Pin Descriptions Table 1-3. I/O Pin Types I/O I Input. High impedance, TTL. O Output. CMOS. I/O Input/Output. TTL input/CMOS output. t/s Three-state. Bidirectional three-state I/O pin. s/t/s Sustained three-state. This is an active-low, three-state signal ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 1-4. CN8478 Hardware Signal Definitions ( MQFP Pin Label Signal Name Pin No. 190 ECLK Expansion Bus Clock 144-146, EAD[31:0] Expansion Bus 149-152, Address and Data 154-155, 158-163, 166-170, 173-174, 176-180, ...

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System Description 1.1 Pin Descriptions Table 1-4. CN8478 Hardware Signal Definitions ( MQFP Pin Label Signal Name Pin No. 117, 122, TCLK[7:0] Transmit Clock 125, 128, 131, 136, 140, 143 116, 121, TSYNC[7:0] Transmit 124, 127, Synchronization ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 1-4. CN8478 Hardware Signal Definitions ( MQFP Pin Label Signal Name Pin No 10, RDAT[7:0] Receive Data 16, 20, 24, 30 11, ROOF[7:0] Receiver 17, 21, ...

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System Description 1.1 Pin Descriptions Table 1-4. CN8478 Hardware Signal Definitions ( MQFP Pin Label Signal Name Pin No. 48-51, 54, AD[31:0] PCI Address 56-58, 61, and Data 65-66, 69-72, 88, 90-94, 97, 99, 101-103, 105-109 43 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 1-4. CN8478 Hardware Signal Definitions ( MQFP Pin Label Signal Name Pin No. 80 DEVSEL* PCI Device Select 60 IDSEL PCI Initialization Device Select 85 SERR* System Error 84 PERR* Parity ...

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System Description 1.1 Pin Descriptions Table 1-4. CN8478 Hardware Signal Definitions ( MQFP Pin Label Signal Name Pin No. 35 TCK JTAG Clock 36 TRST* JTAG Reset 37 TMS JTAG Mode Select 38 TDO JTAG Data Output ...

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Host Interface MUSYCC’s host interface performs the following major functions: • Transfers data between the serial interface and shared memory over the • Bridges system host processors to the devices connected to the EBUS • Stores configuration state information ...

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Host Interface 2.1 PCI Interface 2.1 PCI Interface The host interface in MUSYCC is compliant with the PCI Local Bus Specification (Revision 2.1, June 1, 1995). MUSYCC provides a PCI interface specific to 3.3 V and ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 2.1.2 PCI Bus Operations MUSYCC behaves either as a PCI master or a PCI slave at any time and switches between these modes as required during device operation PCI slave, MUSYCC responds ...

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Host Interface 2.1 PCI Interface The address phase during a MUSYCC configuration cycle indicates the function number and register number being addressed which can be decoded by observing the status of the address lines AD[31:0]. lines during the configuration ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 2-1. Function 0 Configuration Space Register Byte Offset Number (Hex) 0 00h 1 04h 2 08h 3 0Ch 4 10h 5 14h — — 14 38h 15 3Ch NOTE(S): (1) Registers shared between ...

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Host Interface 2.1 PCI Interface In summary, both configuration spaces have unique registers except for the Device ID, Vendor ID, and Revision ID, which are shared between the configuration spaces for Functions 0 and 1. MUSYCC is a multifunction ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 2.2 PCI Configuration Registers 2.2.1 Function 0 Network Controller—PCI Master and Slave MUSYCC provides the necessary configuration space for a PCI bus controller to query and configure MUSYCC’s PCI interface. PCI configuration space consists ...

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Host Interface 2.2 PCI Configuration Registers Register 1, Address 04h The Status register records status information for PCI bus related events. The Command register provides coarse control to generate and respond to PCI commands. At reset, MUSYCC sets the ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 2-4. Register 1, Address 04h ( Bit Name Field 15:10 Command active-low signal is denoted by a trailing asterisk (*). ...

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Host Interface 2.2 PCI Configuration Registers Register 2, Address 08h This location contains the Class Code and Revision ID registers. The Class Code register contains the Base Class Code, Sub-Class Code, and Register Level Programming Interface fields, used to ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Register 3, Address 0Ch Table 2-6. Register 3, Address 0Ch Bit Name Field 31 Built-In Self Test (BIST) Capable 30 Start BIST 29:27 Reserved 26 BIST Error in the Interrupt Queue 25 BIST Error ...

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Host Interface 2.2 PCI Configuration Registers Register 4, Address 10h Table 2-7. Register 4, Address 10h Bit Name Field 31:20 MUSYCC - Function 0 Base Address Register 19 active-low signal is denoted by a trailing ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Register 15, Address 3Ch Table 2-9. Register 15, Address 3Ch Bit Name Field 31:24 Maximum Latency 23:16 Minimum Grant 15:8 Interrupt Pin 7:0 Interrupt Line An active-low signal is denoted by a trailing asterisk ...

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Host Interface 2.2 PCI Configuration Registers Register 0, Address 00h Table 2-10. Register 0, Address 00h Bit Name Field 31:16 (1) Device ID 15:0 (1) Vendor ID NOTE(S): (1) Registers shared between Function 0 and 1. Register 1, Address ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 2-11. Register 1, Address 04h ( Bit Name Field 15:7 Command 6 5 active-low signal is denoted by a trailing asterisk (*). NOTE(S): Register 2, Address 08h This ...

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Host Interface 2.2 PCI Configuration Registers Register 3, Address 0Ch Table 2-13. Register 3, Address 0Ch Bit Name Field 31:24 Reserved 23:16 Header Type 15:0 Reserved Register 4, Address 10h Table 2-14. Register 4, Address 10h Bit Name Field ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Register 15, Address 3Ch Table 2-16. Register 15, Address 3Ch Bit Name Field 31:16 Reserved 15:8 Interrupt Pin 7:0 Interrupt Line An active-low signal is denoted by a trailing asterisk (*). NOTE(S): 2.2.3 PCI ...

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Host Interface 2.2 PCI Configuration Registers 2.2.5 PCI Bus Parity The agent driving the AD[31:0] signals during any bus phase must also drive the even parity signal (PAR). PAR is driven one clock after AD[31:0] has been driven as ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) When MUSYCC requests the PCI bus, it needs the bus to transfer data between an internal FIFO buffer and shared memory across the PCI bus with either a read or a write access. While ...

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Host Interface 2.2 PCI Configuration Registers The longest latency MUSYCC experiences in gaining access to the PCI bus the number of PCI masters in the system T = the value of the latency timers ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The predictable worst case time MUSYCC must wait for the bus in a system with k masters with equal latency timers one MUSYCC is configured with all 256 channels active, and ...

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Host Interface 2.2 PCI Configuration Registers 2.2.6.3 Latency When the following is assumed: Computation—Burst • MUSYCC has enough internal buffering to buffer up to 4-dwords worth of Access • MUSYCC has a granularity of 8 for its latency timer ...

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Expansion Bus (EBUS) MUSYCC provides a PCI bridge to a local bus interface on MUSYCC called the Expansion Bus (EBUS). The EBUS provides a host processor across the PCI bus to access peripheral memory ...

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Expansion Bus (EBUS) 3.1 Operation 3.1 Operation 3.1.1 Initialization At initialization, MUSYCC’s PCI Function 1 Configuration Space is initialized with a value representing memory range assigned to MUSYCC’s EBUS. This is detailed in EBUS—Function 1 Base ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The EBUS interface transfers 32 bits of the data lines between the EBUS and the PCI bus. The byte-enable signal lines EBE[3:0]* are transferred from the PCI byte-enable signal lines CBE[3:0]* to the EBUS, ...

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Expansion Bus (EBUS) 3.1 Operation 3.1.4 Interrupt When a device connected to the EBUS drives the EINT* signal, MUSYCC carries this signal through to the PCI interrupt line, INTB*. Thus, peripheral devices can interrupt the host processor. In MUSYCC’s ...

Page 65

CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 3.1.7 Bus Access Interval MUSYCC can be configured to wait a specified amount of time after it releases the EBUS and before it requests the EBUS a subsequent time. This is accomplished by specifying ...

Page 66

Expansion Bus (EBUS) 3.1 Operation 3.1.9 Microprocessor Interface The MPUSEL bit field specifies the type of microprocessor interface to use for the EBUS. (See Table 3-1 Table 3-1. Intel Protocol Signals Signal ALE* RD* WR* HOLD HLDA NOTE(S): 3-6 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 3-2 selected. Table 3-2. Motorola Protocol Signal Signal AS* DS* R/WR* BR* BG* BGACK* NOTE(S): 3.1.10 Arbitration The HOLD and HLDA (Intel style) or BR* and BG* (Motorola style) signal lines are used ...

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Expansion Bus (EBUS) 3.1 Operation For Motorola-style interfaces, the arbitration protocol is as follows (refer to Figure 7-14, EBUS Write/Read Transactions 10. 11. 12. 3.1.11 Connection Using the EBUS address ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 3-5. EBUS Connection, Non-multiplexed Address/Data, 61 Framers, No MPU EAD[31:24] EAD[23:16] EAD[31:0] EAD[15:8] EAD[7:0] EAD[8:0] EINT* EAD[10,9] Control Lines Dev 0, Bank 0 EBE[3:0] Chip Select Logic 8478_011 NOTE(S): 1. EBEx[3:0]* selects device ...

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Expansion Bus (EBUS) 3.1 Operation Figure 3-6. EBUS Connection, Multiplexed Address/Data, 8 Framers, No MPU EAD[8:0] EINT* AS*, RWR*, DS*, ECLK Control Lines 2:4 Decoder EAD[10:9 ALE EBE[0] 8478_012 3-10 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Data ...

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Serial Interface Each serial interface consists of Serial Port Interfaces (SERI), Bit Level Processors (BLP), Direct Memory Access Controllers (DMAC), and an Interrupt Controller (INTC). A separate set of SERI, BLP, and DMAC services receive channels and transmit channels ...

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Serial Interface 4.1 Serial Port Interface 4.1 Serial Port Interface A receive serial port interface (Rx-SERI) connects to four input signals: RCLK, RDAT, RSYNC, and ROOF. A transmit serial port interface (Tx-SERI) connects to two input signals and one ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 4.5 Channelized Port Mode Each SERI can be configured independently using the PORTMD bit field (see Table 5-12, Port Configuration Channelized mode refers to a data bit stream segmented into frames. Each frame consists ...

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Serial Interface 4.5 Channelized Port Mode supporting an Nx8 bit rate between 8 kbps to 64 kbps in multiples of 8 kbps. The following configurations are required to support subchannels: • Each active bit is assigned a logical channel ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 4-2. Transmit and Receive T1 Mode RCLK RSYNC-RISE(a) RDATA-RISE(a) RSYNC-RISE(b) RDAT-FALL(b) 6 RSYNC-FALL(c) RDATA-RISE(c) RSYNC-FALL(d) RDAT-FALL(d) 6 TCLK TSYNC-RISE(a) TDAT-RISE(a) 6 TSYNC-RISE(b) TDATA-FALL(b) TSYNC-FALL(c) TDAT-RISE(c) 6 TSYNC-FALL(d) TDATA-FALL(d) 8478_014 NOTE(S Mode ...

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Serial Interface 4.5 Channelized Port Mode Figure 4-3. Transmit and Receive E1 (also 2xE1, 4xE1) Mode RCLK RSYNC-RISE(a) RDATA-RISE(a) RSYNC-RISE(b) RDAT-FALL(b) 6 RSYNC-FALL(c) RDATA-RISE(c) RSYNC-FALL(d) RDAT-FALL(d) 6 TCLK TSYNC-RISE(a) TDAT-RISE(a) 6 TSYNC-RISE(b) TDATA-FALL(b) TSYNC-FALL(c) TDAT-RISE(c) 6 TSYNC-FALL(d) TDATA-FALL(d) 8478_015 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 4-4. Transmit and Receive Nx64 Mode RCLK RSYNC-RISE(a) RDATA-RISE(a) RSYNC-RISE(b) RDAT-FALL(b) 6 RSYNC-FALL(c) RDATA-RISE(c) RSYNC-FALL(d) RDAT-FALL(d) 6 TCLK TSYNC-RISE(a) TDAT-RISE(a) 2 TSYNC-RISE(b) TDATA-FALL(b) TSYNC-FALL(c) TDAT-RISE(c) 2 TSYNC-FALL(d) TDATA-FALL(d) 8478_016 NOTE(S): 1. Nx64 Mode ...

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Serial Interface 4.5 Channelized Port Mode 4.5.4 Change-of-Frame Alignment A Change of Frame Alignment (COFA) condition is defined as a frame synchronization event detected when it is not expected, and includes the detection of the first occurrence of frame ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 4.6 Serial Port Mapping MUSYCC contains up to eight serial ports with each port associated to a channel group processor that supports logical bidirectional channels. To manage more than 32 logical ...

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Serial Interface 4.6 Serial Port Mapping The following port mappings are available: • PORTMAP = 0, 1x port mode • PORTMAP = 1, 2x port mode • PORTMAP = 2, 4x port mode Mapping a serial port to one ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 4.7 Tx and Rx FIFO Buffer Allocation and Management Each channel group contains a separate internal buffer memory space for transmit and receive operations. Within each of these spaces, separate areas are set aside ...

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Serial Interface 4.7 Tx and Rx FIFO Buffer Allocation and Management Figure 4-7. Transmit Data Flow Transmit BLP Channel 8478_019 1/2 FIFO = BUFFLEN+1 NOTE(S): The allocation of internal data buffers requires an understanding of how the total available ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 4.7.1 Example Channel BUFFLOC and BUFFLEN Specification With some subchanneling, only the Fixed Data Buffer (total of 64 dwords) is the area available for Internal Data Buffer usage. If the buffer space is evenly ...

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Serial Interface 4.7 Tx and Rx FIFO Buffer Allocation and Management With no subchanneling, the Fixed Data Buffer area plus the Subchannel Map area are available for Internal Data Buffer usage (total of 128 dwords). If the buffer space ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 4.7.2 Receiving Bit Stream As a receive channel is activated, MUSYCC reads in descriptors from shared memory and prepares Rx-BLP and Rx-DMAC to service incoming serial data accordingly, assuming all configurations are proper, and ...

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Serial Interface 4.7 Tx and Rx FIFO Buffer Allocation and Management 4.7.3.1 Transmit Data The TDAT signal from MUSYCC is the only output signal in the serial interface. Bit Output Value For each bit time specified by the TCLK ...

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Memory Organization MUSYCC interfaces with a system host using a set of data structures located in a shared memory region. MUSYCC also contains a set of internal registers which the host can configure and which controls MUSYCC. This section ...

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Memory Organization 5.1 Memory Architecture Figure 5-1. Shared Memory Model Per Channel Group Group Base Pointer Channel Group Descriptor Tx Head Pointer – Head Pointer – Ch..... Tx Head Pointer – Message Pointer ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.1.1 Register Map Access and Shared Memory Access During MUSYCC’s PCI initialization, the system controller allocates a dedicated 1 MB memory range to each of MUSYCC’s PCI functions. The memory range allocated to MUSYCC ...

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Memory Organization 5.1 Memory Architecture The 1 MB memory ranges assigned to MUSYCC functions will not restrict MUSYCC’s PCI interface from attempting to access these ranges. The host must be cognizant that MUSYCC cannot respond to an access cycle ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The first four registers in each group (shown in bold-type in located exclusively within MUSYCC. These registers are accessed by the host using direct reads and writes to the corresponding register map address. The ...

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Memory Organization 5.1 Memory Architecture The first four sets of pointers for each channel group, listed in Table 5-2, Group Structure Memory Map, are pointer locations exclusive to shared memory. MUSYCC does not keep these values internally although they ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The Base Address is written into MUSYCC by the host-initiated PCI configuration access write cycles. After MUSYCC functions are memory-mapped to PCI space, the host allocates shared memory space for each supported channel group ...

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Memory Organization 5.1 Memory Architecture Next, the host allocates the required shared memory for transmit and receive messages. Assume, for example, the host needs 8 message descriptors for each channel and direction, and each corresponding data buffer per message ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.2 Descriptors This section further details the descriptors specified in the MUSYCC memory model. The MUSYCC descriptors are as follows Each of the above entities are allocated, deallocated, read ...

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Memory Organization 5.2 Descriptors 5.2.1 Host Interface Level Descriptors Host interface-level descriptors contain information necessary to configure the global registers. This information applies to the entire device, including all channel groups, serial ports, and channels. 5.2.1.1 Global The Global ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-6. Global Configuration Descriptor ( Bit Name Value Field 10 MPUSEL 0 1 9:8 ALAPSE[1:0] 0–3 7 RSVD 0 6:4 ELAPSE[2:0] 0–7 3 INTAMSK INTBMSK 0 1 1:0 ...

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Memory Organization 5.2 Descriptors 5.2.1.2 Dual Address MUSYCC supports 32-bit and 64-bit memory addressing. The Dual Address Cycle Base Pointer Cycle Base Pointer (DACBASE) supports 64-bit memory addressing and is described in If the value of DACBASE is 0, ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.2.2.2 Service Request The Service Request is a register per channel group within the host interface containing a bit field where instructions are written to MUSYCC by the host. The following instructions are supported: ...

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Memory Organization 5.2 Descriptors Table 5-9. Service Request Descriptor ( Bit Name Value Field 31:13 RSVD 0 12:8 SREQ[4: 5-14 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Description Reserved. No Operation. This ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-9. Service Request Descriptor ( Bit Name Value Field 12:8 SREQ[4:0] 6– 12– 22– 27–31 7:6 RSVD 0 ...

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Memory Organization 5.2 Descriptors 5.2.2.3 Group The Group Configuration Descriptor contains configuration bits applying to all Configuration Descriptor 32 logical channels within a given channel group as listed in Table 5-10. Group Configuration Descriptor ( Bit Name ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-10. Group Configuration Descriptor ( Bit Name Value Field 6 MCENBL MSKCOFA MSKOOF OOFABT SUBDSBL TXENBL ...

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Memory Organization 5.2 Descriptors 5.2.2.4 Memory The memory protection function is not implemented. This function must be Protection Descriptor disabled by clearing the PROTENBL bit in the Memory Protection Descriptor. Table 5-11 Table 5-11. Memory Protection Descriptor Bit Name ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-12. Port Configuration Descriptor Bit Name Value Field 31:10 RSVD 0 9 TRITX ROOF_EDGE RSYNC_EDGE RDAT_EDGE TSYNC_EDGE TDAT_EDGE ...

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Memory Organization 5.2 Descriptors 5.2.2.6 Message Length Each channel group can have two separate values for maximum message length: Descriptor MAXFRM1 or MAXFRM2 (see 4,094 octets. The minimum message length is either depending on non-FCS ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Numerous mappings of time slots to channels are possible. Multiple time slots can be mapped to a single channel; however, each time slot can map to only one channel at a time. When the ...

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Memory Organization 5.2 Descriptors Table 5-14 lists the value and description of each time slot descriptor. Table 5-14. Transmit or Receive Time Slot Map Byte Offset 00h ... 1Ch ... 3Ch ... 5Ch ... 7Ch Accessing the Time Slot ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The host can read and write the Receive Time Slot Map information from within MUSYCC; however, the host can only write Transmit Time Slot Map into MUSYCC. The transmit maps are stored in write-only ...

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Memory Organization 5.2 Descriptors 5.2.2.8 Subchannel Map To provide the subchanneling feature, MUSYCC shares the time slot mapping function between a Time Slot Map and a Subchannel Map. The transmit and receive functions each have a separate pair of ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-16. Transmit or Receive Subchannel Map Byte Offset 00h 04h 08h 0Ch ... ... F8h FCh Table 5-17. Subchannel Descriptor Bit Field Name 31 BITEN3/7 30:29 RSVD 28:24 CH3[4:0] 23 BITEN2/6 22:21 RSVD ...

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Memory Organization 5.2 Descriptors Accessing the Time Slot Map or Subchannel Map within MUSYCC requires that a serial line clock be present at the serial interface clock is not present, writes are ignored, and reads return all ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-18. Channel Configuration Descriptor ( Bit Name Value Field 14:12 PROTOCOL[2: 4–7 11:10 MAXSEL[1: FCS MSKSUERR ...

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Memory Organization 5.2 Descriptors Table 5-18. Channel Configuration Descriptor ( Bit Name Value Field 14:12 PROTOCOL[2: 4–7 11:10 MAXSEL[1: FCS MSKSUERR MSKSINC ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-18. Channel Configuration Descriptor ( Bit Name Value Field 3 MSKMSG MSKEOM MSKBUFF RSVD 0 5.2.4 Message Level Descriptor One message descriptor ...

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Memory Organization 5.2 Descriptors A message descriptor is designed to be usable by both the transmit and receive functions in MUSYCC. In providing this symmetry, a mechanism known as self-servicing buffers is available, which allows the reuse of a ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.2.4.2 Note for An interrupt from MUSYCC does not imply that MUSYCC read a buffer status Interrupt Driven Drivers descriptor and made it host-owned. As mentioned in Note (2) in interrupt and a buffer ...

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Memory Organization 5.2 Descriptors 5.2.4.5 Message The Message Descriptor is pointed to by the Message Pointer and the Head Descriptor Pointer and is maintained in a variable location in shared memory. A Message Descriptor includes the following fields: • ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Tables 5-22 definitions. Table 5-22. Transmit Buffer Descriptor Bit Name Value Field 31 OWNER 0 HOST Owns Buffer. HDLC channel remains in idle mode while polling this bit periodically ( until ...

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Memory Organization 5.2 Descriptors Table 5-23. Receive Buffer Descriptor Bit Name Value Field 31 OWNER RSVD 0 28 EOBI 0 1 27:14 RSVD 0 13:0 BLEN[13:0] 5.2.4.7 Buffer Status The Buffer Status ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Tables 5-24 their descriptions. Table 5-24. Transmit Buffer Status Descriptor Bit Name Value Field 31 OWNER RSVD 0 29 EOM 0 1 28:14 RSVD 0 13:0 BLEN[13:0] 100660E and 5-25 list ...

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Memory Organization 5.2 Descriptors Table 5-25. Receive Buffer Status Descriptor Bit Name Value Field 31 OWNER RSVD 0 29 EOM 0 1 28:20 RSVD 0 19:16 ERROR[3: 3– ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.2.4.8 Next Message The Next Message Pointer is a 32-bit dword-aligned address pointing to the first Pointer dword of a Message Descriptor which is next in a list of descriptors. Table 5-26 Message Pointer ...

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Memory Organization 5.2 Descriptors 5.2.5 Interrupt Level Descriptors MUSYCC generates interrupts for a variety of reasons. Interrupts are events or errors detected by MUSYCC during bit-level processing of incoming serial data streams. Interrupts are generated by MUSYCC and forwarded ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.2.5.2 Interrupt The Interrupt Descriptor describes the format of data transferred into the queue. Descriptor This 32-bit word includes bit fields for the following: • Identifying the interrupt source from within MUSYCC. Channel group ...

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Memory Organization 5.2 Descriptors The following items are issued separately in their own interrupt descriptors: Items Issued Separately • Events: • Errors: In the list below, a single event can combine with a single error within the same Items ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-31. Interrupt Descriptor ( Bit Field Interrupt Value Field Name Name 31 DIR 0 1 30:29 GRP[1:0] 0–3 28:24 CH[4:0] 0–31 23:20 EVENT[3:0] 0 NONE 1 SACK 2 EOB 3 EOM ...

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Memory Organization 5.2 Descriptors Table 5-31. Interrupt Descriptor ( Bit Field Interrupt Value Field Name Name 19:16 ERROR[3:0] 0 NONE 1 BUFF 2 COFA 3 ONR 4 PROT 5-7 8 OOF 5-42 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 5-31. Interrupt Descriptor ( Bit Field Interrupt Value Field Name Name 19:16 ERROR[3:0] 9 FCS 10 ALIGN 11 ABT 12 LNG 13 SHT 14 SUERR 15 PERR 15 ILOST 0 ILOST ...

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Memory Organization 5.2 Descriptors Table 5-31. Interrupt Descriptor ( Bit Field Interrupt Value Field Name Name 14 GRP[2] 13:0 BLEN[13:0] NOTE(S): (1) Receive EOB and Receive EOM are concurrent events and are reported as a single interrupt; ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 5.2.6 Interrupt Handling 5.2.6.1 Initialization Interrupt management resources are automatically reset upon the following: • Hardware reset • Soft-chip reset service request • Global initialization service request • Read Interrupt Queue Descriptor service request ...

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Memory Organization 5.2 Descriptors In cases where both shared memory queue and internal queue are full and new descriptors are generated, those descriptors are discarded. MUSYCC indicates it has lost interrupts internally by overwriting the bit field ILOST in ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The Figure 5-2. Interrupt Notification To Host External Logic Device on EBUS Drives Interrupt Line 8478_022 100660E Figure 5-2 illustrates the operation of EINT*. MUSYCC INTB* EINT* INTA* Internal Logic Unserviced Interrupt Descriptors in ...

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Memory Organization 5.2 Descriptors 5-48 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Conexant 100660E ...

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Basic Operation 6.1 Reset There are five levels of reset state: • Hard PCI Reset • Soft Chip Reset • Soft Group Reset • Channel Activation • Channel Deactivation There are two ways to assert a reset ...

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Basic Operation 6.1 Reset 6.1.2 Soft Chip Reset A Soft Chip Reset (SCR device-wide reset without the host interface’s PCI state being reset. Serial interface operations and EBUS operations are stopped. The soft chip reset state is ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.1.3 Soft Group Reset Every supported channel group within MUSYCC has the ability to reset (or deactivate) a specific direction for all channels in the group using a single service request: the soft group ...

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Basic Operation 6.2 Configuration 6.2 Configuration A sequence of hierarchical initializations must occur after resets. The levels of hierarchy are as follows 6.2.1 PCI Configuration After power- PCI reset sequence, MUSYCC enters a ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.2.2 Global Configuration After PCI configuration is complete, a set of hierarchical configuration sequences must be executed to begin operation at the channel level. Global configuration is initiated by the host either issuing a ...

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Basic Operation 6.2 Configuration 6.2.6 MUSYCC Internal Memory MUSYCC has two areas of host-accessible internal memories. One is the Internal RAM (IRAM) and is accessed through MUSYCC’s Direct Memory Access Controller (DMAC). The IRAM area contains the following descriptors ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) All of the slave writes can be accomplished with initial service requests after setting the appropriate descriptor value in shared memory. Also, any value that could be read directly from MUSYCC can more easily ...

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Basic Operation 6.3 Channel Operation 6.3 Channel Operation To start any channel processing, a series of shared memory segments must be obtained by the host and initialized as specific descriptors which MUSYCC can use to control its channel processing ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) For this example, the following group structure declaration is used: /* Reference: Chapter “Memory Organization” */ #define SIZE_OF_GROUP_STRUCTURE 1564 #define NUM_GROUPS 1 #define BOUNDARY 2048 #define MUSYCC_FUNC_0_BAR 0x00900000 /* system usually assigns this */ ...

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Basic Operation 6.3 Channel Operation 6.3.2 Group Base Pointer For the Group Base Pointer the host must allocate bound memory segment for Channel Group 0. The value calculated as the address for a Group Base Structure ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.3.3 Global Configuration Descriptor /* CLOCK activity indicators - read only, writes are ignored */ /* MPU control - assume EBUS is not used and default values are fine */ /* PORTMAP = 0, ...

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Basic Operation 6.3 Channel Operation 6.3.4 Interrupt Queue Descriptor #define BYTES_PER_INT_DESCR 4 /* recall, dword = 32-bits or 4 bytes */ #define NUM_INT_DESCR_NEEDED 10 /* assumption (min = 2, max = 32768) */ #define SIZE_OF_INTERRUPT_QUEUE (BYTES_PER_INT_DESCR * NUM_INT_DESCR_NEEDED) #define ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.3.5 Group Configuration Descriptor /* signal unit error threshold = 0, no SS7 support required */ /* sf alignment = 0, use internal flywheel mechanism after initial frame sync */ /* poll throttle = ...

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Basic Operation 6.3 Channel Operation 6.3.6 Memory Protection Descriptor /* memory protection disabled = 0 */ GroupStr0.MemoryProtectDescr = 0x00000000; /* either write directly into MUSYCC register - or - use a service request */ *(MUSYCC_FUNC_0_BAR + GROUP_CONFIG_DESCR_OFFSET) = GroupStr0.MemoryProtectDescr; ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.3.8 Message Length Descriptor /* maximum frame length register 2 = 0x200 */ /* maximum frame length register 1 = 0x400 */ GroupStr0.MessageLengthDescr = 0x02000400; /* either write directly into MUSYCC register - or ...

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Basic Operation 6.3 Channel Operation The components of the Transmit Time Slot map are listed in Table 6-8. Example—Components of Transmit Time Slot Map – Channel 0 Descriptor Component of Descriptor Time Slot TSEN3/7 Map CH3/7 TSEN2/6 CH2/6 TSEN1/5 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) The components of the Transmit Subchannel map are listed in Table 6-9. Example—Components of Transmit Subchannel Map Descriptor Component of Descriptor Subchannel BITEN3/7 Map CH3/7 (dword 4) BITEN2/6 CH2/6 BITEN1/5 CH1/5 BITEN0/4 CH0/4 Subchannel ...

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Basic Operation 6.3 Channel Operation GroupStr0.TxChannelConfigDescr[0] = 0x000024000; /* for logical channel everything same except as logical channel buffer location index = internal buffer length = message ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.3.12 Receive Time Slot Map Same as Transmit Time Slot Map. 6.3.13 Receive Subchannel Map Same as Transmit Subchannel Map. 6.3.14 Receive Channel Configuration Descriptor Same as Transmit Channel Configuration Descriptor. 6.3.15 Message Lists ...

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Basic Operation 6.3 Channel Operation The following describes a general sequence for setting up the transmit Message Descriptor for a single channel: /* assume transmit channel is currently deactivated */ /* assume that a 1024-byte message is separated into ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) pTxMsgDescr[1]->BufferDescr = 0x90000200; /* msg descr 2 */ pTxMsgDescr[2]->BufferDescr = 0x90000200; /* msg descr only difference is EOM bit */ pTxMsgDescr[3]->BufferDescr = 0x92000200; /* fill data buffer with outbound traffic. each ...

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Basic Operation 6.3 Channel Operation 6.3.16.2 Receive The following describes what MUSYCC does when the receive channel is Channel Activation activated 6-22 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Checks bit field ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™ NOTE: 6.3.17 Channel Deactivation After the channel has been activated, channel deactivation via a service request suspends activity on an individual channel-direction by stopping that channel’s processing of the current buffer ...

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Basic Operation 6.3 Channel Operation 6.3.18 Channel Jump A channel jump request is issued by the host via a service request. For a receiver, channel jumps are the same as channel activation. For a transmitter, channel jumps are non-destructive ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) For HDLC mode channels, data stream processing begins immediately upon channel activation. Any type of alignment of a HDLC channel's data stream with respect to its assigned serial port time slots is unnecessary, and ...

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Basic Operation 6.3 Channel Operation The frequency of polling is controlled independently for each channel group by the SFALIGN (superframe alignment) and POLLTH (poll throttle) bit fields in the Group Configuration Descriptor. The SFALIGN bit field defines the source ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) To exit repeat mode after the current message is completely transmitted and before the next repetition (gracefully or non-destructively), a channel jump service request must be issued. Prior to the jump request, the host ...

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Basic Operation 6.4 Protocol Support 6.4 Protocol Support 6.4.1 Frame Check Sequence MUSYCC is configurable to calculate either a 16- or 32-bit Frame Check Sequence (FCS) for HDLC packets ranging in size from a minimum of 2 octets to ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.4.4 Zero-Bit Insertion/Deletion MUSYCC provides 0-bit insertion and deletion when it encounters five consecutive 1s within a frame. In the receiver bit is de-inserted, and in the transmitter a 0 bit is ...

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Basic Operation 6.4 Protocol Support Setting MCENBL to 0 prevents MUSYCC from copying the Message Configuration Bits from the Transmit Buffer Descriptor and has the following effect on transmit channel operations throughout the channel group: • PADEN and PADCNT ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 6-13. Message Configuration Descriptor ( Bit Name Field 24 PADEN 23:16 PADCNT[7:0] 15 REPEAT 14:0 RSVD 6.4.7 Bit-Level Operation Each channel group provides two separate Bit-Level Processors (BLP) to service the ...

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Basic Operation 6.4 Protocol Support The following items apply to all event and error handling as described in the transmit and receive sections which follow: • During bit level operations, events and errors can affect the outcome • If ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.4.8 HDLC Mode MUSYCC supports three HDLC modes. The modes are assigned on a per-channel and direction basis by setting the PROTOCOL bit field within the Channel Configuration Descriptor. The HDLC modes are as ...

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Basic Operation 6.4 Protocol Support Reason: End of Message (EOM] • BLP has transmitted the last bit of a data buffer and the Transmit Buffer Effects: • Interrupt Descriptor in Interrupt Queue with EVENT = EOM, DIR = 1 ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Reason: Change to Abort Code (CHABT) • BLP detected received data changed from pad fill (7Eh) octets to abort Effects: • Interrupt Descriptor in Interrupt Queue with EVENT = CHABT, DIR = 0 • ...

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Basic Operation 6.4 Protocol Support Effects: • Interrupt Descriptor in Interrupt Queue with EVENT = SFILT, DIR = 0 • BLP discards the received message in the FIFO. • BLP and DMAC continue with normal message processing. 6.4.8.3 Transmit ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) In the case of change of frame alignment while transmitting an HDLC message Change of Frame Alignment (T1/E1 modes), the TSYNC input signal transitions from low to high when not (COFA) while Transmitting expected ...

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Basic Operation 6.4 Protocol Support Once a descriptor is granted, however, MUSYCC assumes ownership of the message buffer and continues writing data until the end of buffer is reached. If the host reclaims the buffer without MUSYCC granting ownership ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Channel Level Recovery Actions: • If possible, increase internal FIFO buffer space for this channel. For this • If required, alleviate congestion of the PCI bus. • Change of Frame Alignment (COFA) while Receiving ...

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Basic Operation 6.4 Protocol Support Out-of-frame or loss-of-frame indicates that the entire serial data stream is invalid Out of Frame (OOF) and data cannot be recovered from such a signal. In this case, out-of-frame of the incoming signal occurred ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) In the case of an Octet Alignment (ALIGN) error, the HDLC message size after Octet Alignment (ALIGN) 0-bit extraction is not a multiple of 8 bits. Error Reasons: • Bit errors during transmission. • ...

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Basic Operation 6.4 Protocol Support In the case of a Long Message (LNG) error, the received HDLC message size is Long Message (LNG) determined to be greater than the maximum allowed message size (per MAXSEL in Channel Configuration Descriptor). ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) In the case of an SS7 SUERR, an error is detected in SS7 mode which caused a SS7 Signal Unit Error Rate counter for SS7 related errors to equal or exceed the permitted threshold ...

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Basic Operation 6.4 Protocol Support If the host wants to send any more data on that channel, the host must reactivate any transparent mode transmit channel that has issued an ONR error. Notice there is no mechanism for transparent ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.4.9.3 Transmit Errors Transmit Errors are service-affecting and require a corrective action by the host to resume normal bit-level processing. In the case of underflow due to host ownership of buffer (ONR), sufficient data ...

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Basic Operation 6.4 Protocol Support 6.4.9.4 Receive Errors Receive errors are service-affecting and may require a corrective action by a controlling device to resume normal bit-level processing. In the case of overflow due to host ownership of the buffer, ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) In the case of a Change of Frame Alignment while receiving an HDLC message Change of Frame Alignment (T1/E1 modes (T1/E1 Modes) (COFA) unexpectedly by the “frame synchronization flywheel mechanism.” This error applies only ...

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Basic Operation 6.4 Protocol Support 6.4.10 Intersystem Link Protocol (ISLP) ISLP is supported by setting the following bit field value referenced in Table 5-18, Channel Configuration FCS = 1, PROTOCOL = 2 6-48 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.5 Signaling System 7 6.5.1 SS7 Repeat Message Transmission Signaling System 7 (SS7) requires the ability to continuously repeat a message under certain circumstances. The Repeat Message Transmission section of this document describes the ...

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Basic Operation 6.5 Signaling System 7 6.5.3 Signal Unit Error Rate Monitoring The Signal Unit Error Rate Monitor (SUERM) facility provides a 6-bit counter which serves as a real-time figure-of-merit for the receive link integrity incremented and ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 6.6 Self-Servicing Buffers The transmit and receive Buffer Descriptors and Buffer Status Descriptors are designed to facilitate a mechanism known as “self-servicing buffers.” This mechanism allows the host to configure MUSYCC to fill a ...

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Basic Operation 6.6 Self-Servicing Buffers 6-52 CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Conexant 100660E ...

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Electrical and Mechanical Specifications 7.1 Electrical and Environmental Specifications 7.1.1 Absolute Maximum Ratings Stressing the device parameters above absolute maximum ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device ...

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Electrical and Mechanical Specifications 7.1 Electrical and Environmental Specifications 7.1.2 Recommended Operating Conditions Table 7-2. Recommended Operating Conditions Parameter Supply Voltage Ambient Operating Temperature EPF High-Level Input Voltage Low-Level Input Voltage High-Level Output Current Source Low-Level Output Current Sink ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 7.2 Timing and Switching Specifications 7.2.1 Overview The major subsystems of MUSYCC are the host interface, the expansion bus interface, and the serial interface. The host interface is PCI compliant. For other references to ...

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Electrical and Mechanical Specifications 7.2 Timing and Switching Specifications Table 7-4. PCI Interface DC Specifications ( Symbol Parameter V (3) Output Low Voltage ol C Input Pin Capacitance in C CLK Pin Capacitance clk C IDSEL Pin ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 7-6. PCI Clock (PCLK) Waveform Parameters, 66 MHz PCI Clock Symbol Parameter T (1) Clock Cycle Time cyc T Clock High Time high T Clock Low Time low — (2) Clock Slew Rate ...

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Electrical and Mechanical Specifications 7.2 Timing and Switching Specifications Table 7-7. PCI Reset Parameters Symbol Parameter T Reset Active Time after rst Power Stable T Reset Active Time after rst_clk Clock Stable V ( Nominal Voltage Level nom — ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 7-8. PCI I/O Timing Parameters, 33 MHz PCI Clock Symbol Parameter T PCLK to Signal Valid Delay—Bused Signal val T (ptp) PCLK to Signal Valid Delay—Point To Point val T (3) Float to ...

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Electrical and Mechanical Specifications 7.2 Timing and Switching Specifications Table 7-10. PCI I/O Measure Conditions Symbol V Voltage Threshold High th V Voltage Threshold Low tl V Voltage Test Point test V Maximum Peak-to-Peak max — Input Signal Edge ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Figure 7-4. PCI Input Timing Waveform CLK Input 8478_027 Figure 7-5. PCI Read Multiple Operation PCLK FRAME* CBE[3:0] Command AD[31:0] Address PAR IRDY* TRDY* DEVSEL* 8478_028 100660E 7.0 Electrical and Mechanical Specifications T T ...

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Electrical and Mechanical Specifications 7.2 Timing and Switching Specifications Figure 7-6. PCI Write Multiple Operation PCLK FRAME* CBE[3:0] Command AD[31:0] Address PAR IRDY* TRDY* DEVSEL* 8478_029 Figure 7-7. PCI Write Single Operation PCLK FRAME* CBE[3:0] Command AD[31:0] Address PAR ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) 7.2.3 Expansion Bus (EBUS) Timing and Switching Characteristic The EBUS timing is derived from the PCI clock (PCLK) input to MUSYCC. The ECLK output is either one-half of the PCI clock (M66EN = 1) ...

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Electrical and Mechanical Specifications 7.2 Timing and Switching Specifications Figure 7-10. EBUS Reset Timing PCI Reset EBUS Three-state Output EBUS Input 8478_032 The EBUS reset is dependent on the PRST* (PCI Reset) signal being asserted low. NOTE(S): Table 7-12. ...

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CN8478/CN8474A/CN8472A/CN8471A Multichannel Synchronous Communications Controller (MUSYCC™) Table 7-13. EBUS I/O Measure Conditions Symbol V Voltage Threshold High th V Voltage Threshold Low tl V Voltage Test Point test V Maximum Peak-to-Peak max — Input Signal Edge Rate NOTE(S): (1) The ...

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Electrical and Mechanical Specifications 7.2 Timing and Switching Specifications 7.2.4 EBUS Arbitration Timing Illustrated in transactions. Figure 7-13. EBUS Write/Read Transactions, Intel-Style See Notes ECLK HOLD HLDA EAD[31:0] EBE[3:0]* ALE RD* (write) WR* (write) RD* (read) WR* (read) 8478_035 ...

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