cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 44

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

Detailed Functional Description
3.4.2.2
Table 3-17. Pixel Frequency Modes
3-18
BT.656
525-line square pixel
625-line square pixel
Mode
Table 3-16. AFE Control Auto-Config
INPUT_MODE
DUAL_MODE_ADC2
DROOP_COMP_CH3
DROOP_COMP_CH2
CLAMP_EN_CH3
CLAMP_EN_CH2
VGA_SEL_CH3
VGA_SEL_CH1
HALF_BW_CH3
HALF_BW_CH2
Field Name
Pixel Frequency (MHz) 8x Video PLL Frequency (MHz)
Table 3-16
Configuration and AFE Control (N) registers will be configured based on the
INPUT_MODE field of the Video Mode Control 2 register (0x0401).
Video PLL Auto-Config
Similar to the AFE Control Auto-Config feature, the Video PLL frequency is also
automatically configured based on the video operating mode. The Video PLL must be
programmed to eight times the pixel rate. The pixel rate in turn depends on whether
the chip is in square pixel mode, and if so, whether it is currently decoding a 525-line
format or a 625-line format.
When auto-config is enabled, the video PLL frequency will be automatically
configured based on whether the chip is in square pixel mode, and if so, whether the
decoder is decoding a 525-line or 625-line format. The auto-config logic will
immediately re-program the video PLL frequency controls whenever either of the
following events happens:
If desired by the customer, software may overwrite any fields that were set by the
auto-config logic by directly writing to that field. However, the auto-config logic will
again modify the register fields if one of the auto-config events listed above happens.
To disable the auto-config feature altogether, write the CHIP_ACFG_DIS
1.
2.
The SQ_PIXEL bit 4 in Video Mode Control 1 (address = 0x400) is written;
The video format changes, whether due to a register write to the VID_FMT_SEL
field bits 3:0 of Video Mode Control 1, or due to a format change while in auto-
detection mode.
13.5000
12.2727
14.7500
shows how the register field in the Miscellaneous Chip Control
Register
0x401
0x102
0x106
0x106
0x106
0x106
0x105
0x104
0x104
0x104
Bits
2:1
Conexant
2
4
3
1
0
0
6
5
4
(Default)
CVBS
108.0000
118.0000
98.1818
00
0
0
0
0
0
1
1
0
0
Y/C
01
0
0
0
0
0
0
0
0
0
Y/C/A
10
1
0
1
0
0
1
0
0
0
Sq_pixel bit
0
1
1
Y/Pb/Pr
11
1
1
1
1
1
0
0
1
1
CX25840/1/2/3 Data Sheet
Lines-per-frame
Don’t-care
525
625
102284B
8/3/05