cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 42

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

Detailed Functional Description
3.4.1
3-16
Video Signal Format
The input waveform to the video decoder can be in either composite (CVBS), S-Video
(Y/C), or component (YPbPr) format. For any of the composite video inputs, only
ADC1 and ACD2 can be used to sample the video waveform. If desired, the analog
front-end of channel 2 can be powered down in situations that do not require S-Video
or component video decoding. When an S-Video signal is applied, ADC1 samples the
luma signal, and ADC2 samples the chroma signal. When a component waveform
signal is applied, the Pb and Pr values are interleaved on ADC2.
The selection of the type of video format to decode is made by programming the
appropriate value to the INPUT_MODE bits of the Video Mode Control 2 register
(0x401). Once INPUT_MODE is programmed, the video format registers in
Table 3-12
well. In cases where S-Video or component formats are to be decoded, the VGA for
the chroma channels must be programmed to clamp at the mid-code of the input
waveform. This is programmed through the CLAMP_SEL_CHx bits in the AFE
Control 2 register (0x105). Additionally, for decoding component signals, the second
ADC must be programmed for dual sampling mode. The DUAL_MODE_ADC2 bit
of the Miscellaneous Chip Control Configuration register (0x102) should be set high
to enable multiplexed sampling for the Pb and Pr inputs.
For reducing the integrated anti-alias filter bandwidth on chroma channels, the
HALF_BW_CH{1}/2/3 bits are provided. Setting this bit high halves the input
bandwidth for that particular channel and prevents the occurrence of any anti-aliasing
artifacts. This bit should be set when the channels are used for the chroma waveforms
in component video
For power savings measures, the analog front-end associated with chroma inputs can
be powered down when decoding only composite input signals. Control over powering
down the second ADC and its associated VGAs can be found in the Power Control 1
register (0x130).
Table 3-14. Video Format Register Settings
Composite
S-Video
Component
Format
Video
are auto programmed. These registers can be manually programmed as
INPUT_M
ODE
00
01
11
format.Table 3-14
Conexant
CLAMP_S
EL_CH{1}
0
0
0
CLAMP_S
lists the video format register settings.
EL_CH{2}
0
1
1
CLAMP_S
EL_CH{3}
0
1
1
DUAL_MO
DE_ADC2
CX25840/1/2/3 Data Sheet
0
0
1
HALF_BW
_CH{2}/3
102284B
0
0
1
8/3/05