cx25840 Conexant Systems, Inc., cx25840 Datasheet - Page 88

• Manufacturer Part Number: cx25840
• Description: Video Decoder And Broadcast Audio
• Manufacturer: Conexant Systems, Inc.

Detailed Functional Description
3.8.3.1
3.8.4
3-62
IR FIFOs
Transmit Data Modulation
If modulation is enabled, marks are represented by bursts of high frequency carrier
transitions, and spaces are represented by the absence of carrier transitions. The duty
cycle of the high-frequency transitions is programmable. Again, if modulation is
enabled, the TX clock frequency must be 16 times the desired frequency of the carrier
transitions. This 16-bit IR Transmit Clock Divider bit field is used to control the IR
port’s transmit clock rate. The transmit clock is used to drive both the modulation
logic and the transmit pulse width timer. This bit field is used as the modulus for a 16-
bit down counter, which is decremented at half the video clock rate (108 MHz/2).
Each time the counter reaches 0 or the IR TX Clock Divider registers (0x204 and
0x205) are written, the contents of this register are reloaded to the counter. Each time
the counter wraps to 0, a transmit clock pulse is signaled to the modulation logic and
the TX pulse width timer.
If modulation is enabled, this field must be programmed such that the TX clock rate is
16 times the desired carrier frequency when a mark is transmitted. If modulation is
disabled, a clock frequency can be selected such that the longest pulse duration does
not cause the 18-bit TX pulse width timer to overflow. This provides the best
resolution for each pulse that is transmitted. The IR TX Clock Divider bit fields can
be programmed with any value from 0x01 to 0xFFFF. The Transmit Clock Divider is
reset to a value of 0xFFFF. The TX clock rate, given a set Transmit Clock Divider
value, is calculated using the following equation:
The period of one carrier transmitting is broken into 16 time periods. The duty cycle
register provides a selection of one of 16 different carrier duty cycles. The carrier can
be one TX clock period high and 15 low, two TX clock periods high and 14 low, and
so on. The 4-bit IR TX Carrier Duty Cycle (0x20C) register selects the duty cycle
(high time, then low time duration) of the transmit carrier when signaling a mark. The
TX carrier frequency is established by programming the IR TX Clock Divider
registers as described above. Again, the TX clock must be programmed to be 16 times
the desired frequency of the TX carrier. The IR TX Carrier Duty Cycle value then
selects one of 16 possible duty cycles: one TX clock high and 15 TX clocks low, or
two TX clocks high and 14 TX clocks low, etc. This bit field is ignored if modulation
is disabled.
The IR FIFO (0x23C and 0x23D) registers provide access to the IR port’s transmit and
receive FIFOs. Writes to this register access the top of the transmit FIFO, allowing it
to be filled and count values to be transmitted. A write with a value of 0x0000 to the
Tx FIFO is effectively 0xFFFF+1, or maximum pulse width. Reads of this register
access the bottom of the receive FIFO, allowing incoming pulse width measurements
to be removed. The transmit FIFO is 17 bits wide x 8 entries deep. Bits 15–0 contain
the count value to be loaded to the TX pulse width counter, and bit 16 contains the
state which should be driven to the modulation logic. The receive FIFO is 18 bits wide
x 8 entries deep. Bits 15–0 contain the pulse width measurement from the RX pulse
width counter, bit 16 contains the state of the ir_in pin at the end of the measurement,
and bit 17 is a tag which indicates whether more valid data is present within the FIFO.
TxClkFreq
Conexant
=
(
TxClkDivid
108
2 /
er
+
) 1
CX25840/1/2/3 Data Sheet
102284B
8/3/05