k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 9

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

A0-A7, A9-A11
COMMAND
K4J55323QF-GC
INITIALIZATION
those
Following these requirements, the GDDR3 SDRAM is ready for normal operation.
10 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
BA0, BA1
GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
WDQS
RDQS
1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)
2. Required minimum 100us for the stable power before RESET pin transition to HIGH
4. Minimum 200us delay required prior to applying any executable command after stable power and clock.
5. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be
6. Issue a PRECHARGE ALL command following after NOP command.
7. Issue a dummy MRS command ("00001000100001")
8. Issue a EMRS command (BA1BA0="01") to enable the DLL.
9. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
9. Issue a PRECHARGE ALL command
V
V
RES
CKE
CKE
V
DDQ
REF
DM
DQ
CK
CK
A8
DD
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
brought to HIGH,
20K clock cycles are required to lock the DLL.
be in a High-Z state, all active terminators off, and all DLLs off.
specified may result in undefined operation.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
T=10ns
Power-up:
V
t
ATS
DD
and CK stable
t
ATH
T = 200us
t
t
IS
IS
NOP
T0
t
t
IH
IH
High
High
High
t
CH
t
CL
ALL BANKS
Precharge
All Banks
t
IS
PRE
T1
t
IH
tRP
Load Mode Register
(Dummy MRS)
t
t
t
Dummy
IS
IS
IS
CODE
BAO=L,
BA1 =L
CODE
Ta0
MRS
t
t
t
IH
IH
IH
- 9 -
tMRD
Load Extended
Mode Register
t
t
t
IS
IS
IS
EMRS
CODE
CODE
BAO=H,
BA1 =L
Tb0
t
t
t
IH
IH
IH
tMRD
REF
Load Mode Register
DLL Reset
is applied )
CODE
BAO=L,
BA1 =L
CODE
MRS
Tc0
20K cycle
tMRD
ALL BANKS
Precharge
All Banks
256M GDDR3 SDRAM
t
IS
Td0
PRE
t
IH
tRP
Auto Refresh
Te0
1st
AR
Rev 1.7 (Jan. 2005)
tRFC
Auto Refresh
Tf0
AR
2nd
tRFC
ACT
RA
RA
BA