k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 22

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

COMMAND
BA0, BA1
K4J55323QF-GC
OPERATIONS
BANK/ROW ACTIVATION
a row in that bank must be "opened." This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
to that row, subject to the t
and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command in which a READ or WRITE command can be entered. For example, a t
specification of 16ns with a 450MHz clock (2.2ns period) results in 7.2 clocks rounded to 8.
This is reflected in below figure, which covers any case where 7<t
cycles).
the previous active row has been "closed"(precharged). The minimum time interval between
successive ACTIVE commads to the same bank is defined by t
accessed, which results in a reduction of total row access overhead. The minimum time inter-
val between successive ACTIVE commands to different banks is defined by t
Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM,
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued
The same procedure is used to convert other specification limits from tome units to clock
A subsequent ACTIVE command to a different row in the same bank can only be issued after
A subsequent ACTIVE command to another bank can be issued while the first bank is being
A0-A11
/CK
CK
Example : Meeting t
Bank x
ACT
Row
T0
RCD
NOP
T1
RCD
specification. t
t
RRD
NOP
T2
RCD(min)
should be divided by the clock period
Bank y
ACT
Row
T3
- 22 -
RC
.
RCD(min)
NOP
T4
/t
CK
RRD
t
RCD
≤
8.
.
NOP
T7
256M GDDR3 SDRAM
RCD
RD/WR
Bank y
A0-A11
Activating a Specific Row
Rev 1.7 (Jan. 2005)
BA0,1
/CAS
Col
T8
/RAS
CKE
/CK
/WE
CK
/CS
in a Specific Bank
BA = Bank Address
RA = Row Address
HIGH
DON’T CARE
RA
BA
NOP
T9