k4j55323qf-gc Samsung Semiconductor, Inc., k4j55323qf-gc Datasheet - Page 11

• Manufacturer Part Number: k4j55323qf-gc
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QF-GC
NOTE : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR
the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and
Vss. The value of the resistor must be six times the desired output impedance.
For example, a 240
(within 10 %), the range of RQ is
RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The
output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in progress to compen-
sate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates
do not affect device operation, and all data sheet timing and current specifications are met during an update. To guarantee optimum out-
put driver impedance after power-up, the GDDR3(x32) needs 20us after the clock is applied and stable to calibrate the impedance upon
power-up. The user can operate the part with fewer than 20us, but optimal output impedance is not guaranteed. The value of ZQ is also
used to calibrated the internal address/command termination resisters. The two termination values that are selectable at power up are 1/
2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The two termination values that are select-
able are 1/4 of ZQ and 1/2 of ZQ.
BURST LENGTH
table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE com-
mand. Burst length of 4 only is available. Reserved states should not be used, as unknown operation or incompatibility with future ver-
sions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block
is uniquely selected by A2-Ai when the burst length is set to four (Where Ai is the most significant column address bit for a given config-
uration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmable
burst length applies to both READ and WRITE bursts.
BURST TYPE
This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition
The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match
Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS
Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit A3.
set to zero
Ω
resistor is required for an output impedance of 40
Length
Burst
4
120
Ω
to 360
Starting Column
Ω
A1
(20
0
Address
Ω
Burst Definition
to 60
Ω
A0
0
output impedance).
- 11 -
Ω
. To ensure that output impedance is one sixth the value of RQ
Type= Sequential
Order of Access
within A burst
0 - 1 - 2 - 3
256M GDDR3 SDRAM
Rev 1.7 (Jan. 2005)