em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 95

• Manufacturer Part Number: em78p510nso32j/s
• Description: 8-bit Microprocessor With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
6.16 Instruction Set
Each instruction in the Instruction Set is a 13-bit word divided into an OP code and one
or more operand. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the
execution takes two instruction cycles.
The following are executed within two instruction cycles; "LJMP", "LCALL", or
conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were
tested to be true. Instructions written to the program counter are also executed within
two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
Convention:
r = Register designator that specifies which one of the registers (including operation and general purpose
b = Bit field designator that selects the value for the bit located in the register R and which affects the
k = 8 or 10-bit constant or literal value
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0011
0 0000 0000 0100
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
Binary Instruction
can operate on the I/O register.
registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
operation.
0000
0001
0003
0004
0010
0011
0012
0013
0080
Hex
00rr
00rr
Mnemonic
MOV R,A
WDTC
CLR R
SLEP
CLRA
RETI
NOP
DAA
RET
DISI
ENI
8-Bit Microprocessor with OTP ROM
No Operation
Decimal Adjust A
0 → WDT, Stop oscillator
0 → WDT
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
A → R
0 → A
0 → R
Operation
EM78P510N
Affected
Status
None
None
None
None
None
None
T, P
T, P
C
Z
Z
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