em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 76

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em78p510nso32j/s

Manufacturer Part Number
em78p510nso32j/s
Description
8-bit Microprocessor With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
EM78P510N
8-Bit Microprocessor with OTP ROM
70 •
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the marked state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in
which the least significant bit (LSB) comes first. The data bits are followed by the parity
bit. If present, then the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on the falling edge of the start bit. When two or
three “0” are detected during three samples, it is recognized as normal start bit and the
receiving operation is started.
6.11.1 UART Mode
There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the
addition of a parity bit. The parity bit addition is not available in Mode 3. Figure 6-19
below shows the data format in each mode.
Mode 1
Mode 2
Mode 3
START
1 bit
bit
UMODE
0
0
0
0
1
0
0
1
1
0
D0
PRE
0
1
0
1
X
D1
Figure 6-18 Data Format in UART
Figure 6-19 UART Model
D2
7 or 8 bits
One character or frame
START
START
START
START
START
1
(This specification is subject to change without further notice)
2
3
Product Specification (V1.1) 01.25.2008
4
7 bits DATA
7 bits DATA
8 bits DATA
8 bits DATA
9 bits DATA
5
Dn
6
7
Parity
1 bit
bit
8
STOP
STOP
Parity
bit
9
1 bits
STOP
Parity
10
STOP
STOP
STOP
11
Idle state
(mark)

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