em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 83

• Manufacturer Part Number: em78p510nso32j/s
• Description: 8-bit Microprocessor With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
PA5/SEG5/SO:
PA6/SEG6/SCK:
PA7/SEG7//SS:
Program the same clock rate and clock edge to latch on both the master and slave
The byte received will update the transmitted byte.
The RBF (located in Register 0x0C) will be set as the SPI operation is completed.
Timing is shown in Figure 6-23 and 6-24.
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
Program the same clock rate and clock edge to latch on both the master and slave
The received byte will update the transmitted byte.
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is
Timing is shown in Figure 6-23 and 6-24.
Serial Clock
Generated by a master device
Synchronize the data communication on both the SI and SO pins
The CES (located in Register 0x0D) is used to select the edge to communicate.
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode
Timing is show in Figure 6-23 and 6-24
Slave Select; negative logic
Generated by a master device to signify the slave(s) to receive data
Goes low before the first cycle of SCK appears, and remains low until the last
Ignores the data on the SI and SO pins while /SS is high, because the SO is no
Timing is shown in Figure 6-23 and 6-24.
devices.
(LSB) last
devices.
completed.
communication
(eighth) cycle is completed.
longer driven.
8-Bit Microprocessor with OTP ROM
EM78P510N
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