em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 25

• Manufacturer Part Number: em78p510nso32j/s
• Description: 8-bit Microprocessor With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
6.2.23 Bank 1 RC LCDSCR2 (LCD Segment Control Register 2)
Bit 7: Reserved
Bits 6~0 (SEG22~SEG16): LCD Segment 22~16 Control Bits
6.2.24 Bank 1 RE EIMR (External Interrupt Mask Register)
Bits 7~0 (EXIE7~EXIE0): Interrupt Enable Bit. Enable interrupt source respectively.
External interrupt
INT7~INT0: Pulse less than 2/Fc is eliminated as noise. Pulse more than 4/Fc is
6.2.25 Bank 1 RF EISR (External Interrupt Status Register)
These bits are set to “1” when interrupt occurs respectively.
Bits 7~0 (EXIF7~EXIF0): Interrupt Flag when External Interrupt 7~0 occur
INT Pin Secondary Function Pin
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
EXIE7
EXIF7
Bit 7
Bit 7
Bit 7
-
0 : Disable, functions as normal I/O or other functions
1 : Enable, functions as LCD common driver pins
PB3, SEG11
PB2, SEG10, AD11
PB1, SEG9, AD10
PB0, SEG8, AD9
P77, T1CAP
P76, T1CK
P75, T1OUT, PWM1
P74, SEG18
treated as a trigger signal.
SEG22
EXIE6
EXIF6
Bit 6
Bit 6
Bit 6
SEG21
EXIE5
EXIF5
Bit 5
Bit 5
Bit 5
SEG20
ENI+EXIE7 (EIMR7)
ENI+EXIE6 (EIMR6)
ENI+EXIE5 (EIMR5)
ENI+EXIE4 (EIMR4)
ENI+EXIE3 (EIMR3)
ENI+EXIE2 (EIMR2)
ENI+EXIE1 (EIMR1)
ENI+EXIE0 (EIMR0)
EXIE4
EXIF4
Enable Condition
Bit 4
Bit 4
Bit 4
SEG19
EXIE3
EXIF3
Bit 3
Bit 3
Bit 3
8-Bit Microprocessor with OTP ROM
SEG18
EXIE2
EXIF2
Rising or Falling
Rising or Falling
Rising or Falling
Bit 2
Bit 2
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Bit 2
Edge
SEG17
EXIE1
EXIF1
Bit 1
Bit 1
Bit 1
EM78P510N
Digital Noise
Reject
SEG16
EXIE0
EXIF0
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
Bit 0
Bit 0
Bit 0
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