em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 19

• Manufacturer Part Number: em78p510nso32j/s
• Description: 8-bit Microprocessor With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
6.2.9 Bank 0 R9 (Port 9)
Bits 7~0 (R97~R90): Port 9 8-bit I/O Registers.
6.2.10 Bank 0 RA (Port A)
Bits 7~0 (RA7~RA0): Port A 8-bit I/O Registers
6.2.11 Bank 0 RB (Port B)
Bits 7~0 (RB7~RB0): Port B 8-bit I/O Registers
6.2.12 Bank 0 RC SCCR (System Clock Control Register)
Bit 7: Reserved, fixed to “0”
Bits 6~4 (CLK2~CLK0): Main Clock Select Bit for PLL Mode (code option select)
Bit 3 (IDLE): Idle Mode Enable Bit. This bit will decide SLEP instruction which mode
Bits 2~1: Reserved, fixed to “0”
Bit 0 (CPUS): CPU Oscillator Source Select, 0/1 → sub-oscillator (fs)/ main oscillator
Bit 7
Bit 7
Bit 7
Bit 7
RA7
RB7
R97
0
to go.
IDLE=”0”+SLEP instruction → sleep mode
IDLE=”1”+SLEP instruction → idle mode
(fosc)When CPUS=0, the CPU oscillator select sub-oscillator and the main
oscillator is stopped.
CLK2
0
0
0
0
1
1
1
CLK2
Bit 6
Bit 6
Bit 6
Bit 6
RA6
RB6
R96
CLK1
0
0
1
1
0
0
1
CLK1
Bit 5
Bit 5
Bit 5
Bit 5
RA5
RB5
R95
CLK0
0
1
0
1
0
1
×
CLK0
Bit 4
Bit 4
Bit 4
Bit 4
RA4
RB4
R94
Main Clock
Fs×61/2
Fs×61/4
Fs×122
Fs×244
Fs×366
Fs×488
Fs×61
IDLE
Bit 3
Bit 3
Bit 3
Bit 3
RA3
RB3
R93
8-Bit Microprocessor with OTP ROM
Bit 2
Bit 2
Bit 2
Bit 2
RA2
R92
RB2
0
0.999 MHz (default)
Ex: Fs=32.768K
3.997 MHz
1.998 MHz
7.995 MHz
11.99 MHz
15.99 MHz
499.7kHz
Bit 1
Bit 1
Bit 1
Bit 1
RA1
R91
RB1
0
EM78P510N
CPUS
Bit 0
Bit 0
Bit 0
Bit 0
RA0
R90
RB0
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