em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 20

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em78p510nso32j/s

Manufacturer Part Number
em78p510nso32j/s
Description
8-bit Microprocessor With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
EM78P510N
8-Bit Microprocessor with OTP ROM
14 •
CPU Operation Mode
6.2.13 Bank 0 RD TWTCR (TCC and WDT Timer Control Register)
Bit 7 (WDTE): Watchdog Timer Enable. This control bit is used to enable the watchdog
Bits 6~4 (WPSR2~WPSR0): WDT Prescale Bits
Bit 3 (TCCS): TCC Clock Source Select Bit
WDTE
Bit 7
WPSR2
Bit 6
timer.
0 : Disable WDT function
1 : Enable WDT function
0 : Fm (main clock).
1 : Fs (sub clock: 32.768kHz)
WPSR2
Figure 6-3 CPU Operation Mode
0
0
0
0
1
1
1
1
WPSR1
Bit 5
WPSR1
WPSR0
Bit 4
0
0
1
1
0
0
1
1
(This specification is subject to change without further notice)
TCCS
Bit 3
WPSR0
Product Specification (V1.1) 01.25.2008
0
1
0
1
0
1
0
1
TPSR2
Bit 2
TPSR1
1:1 (Default)
Bit 1
Prescale
1 : 128
1 : 16
1 : 32
1 : 64
1 : 2
1 : 4
1 : 8
TPSR0
Bit 0

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