k4b2g0846b Samsung Semiconductor, Inc., k4b2g0846b Datasheet - Page 5

• Manufacturer Part Number: k4b2g0846b
• Description: 2gb B-die Ddr3 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G04(08/16)46B
1.0 Ordering Information
[ Table 1 ] Samsung 2Gb DDR3 B-die ordering information table
Note :
2.0 Key Features
[ Table 2 ] 2Gb DDR3 B-die Speed bins
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device
1. Speed bin is in order of CL-tRCD-tRP.
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
• 400 MHz f
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-Free
Organization
CAS Latency
128Mx16
tRCD(min)
tRAS(min)
667MHz f
(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
(RZQ : 240 ohm ± 1%)
85°C < T
512Mx4
256Mx8
tCK(min)
tRP(min)
tRC(min)
Operation & Timing Diagram”.
DDQ
Speed
= 1.5V ± 0.075V
CASE
CK
CK
96 balls FBGA - x16
for 1333Mb/sec/pin, 800MHz f
for 800Mb/sec/pin, 533MHz f
< 95 °C
K4B2G0446B-HCF7
K4B2G0846B-HCF7
K4B2G1646B-HCF7
DDR3-800 (6-6-6)
DDR3-800
6-6-6
37.5
52.5
2.5
15
15
6
CK
CK
for 1066Mb/sec/pin,
CASE
for 1600Mb/sec/pin
K4B2G0446B-HCF8
K4B2G0846B-HCF8
K4B2G1646B-HCF8
DDR3-1066 (7-7-7)
85°C, 3.9us at
DDR3-1066
13.125
13.125
50.625
1.875
7-7-7
37.5
7
Page 5 of 61
16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This syn-
chronous device achieves high speed double-data-rate transfer rates of up
to 1600Mb/sec/pin (DDR3-1600) for general applications.
tures such as posted CAS, Programmable CWL, Internal (Self) Calibra-
tion, On Die Termination using ODT pin and Asynchronous Reset .
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V
The 2Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8) and
96ball FBGA(x16)
Note : 1. The functionality described and the timing specifications included
The 2Gb DDR3 SDRAM B-die is organized as a 32Mbit x 4 I/Os x 8banks,
The chip is designed to comply with the following key DDR3 SDRAM fea-
All of the control and address inputs are synchronized with a pair of exter-
K4B2G0446B-HCH9
K4B2G0846B-HCH9
K4B2G1646B-HCH9
DDR3-1333 (9-9-9)
DDR3-1333
in this data sheet are for the DLL Enabled mode of operation.
9-9-9
13.5
13.5
49.5
1.5
36
9
2Gb DDR3 SDRAM
DDR3-1600
Rev. 1.0 December 2008
DDR3-1600
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
78 FBGA
78 FBGA
96 FBGA
Package
DDQ
Unit
nCK
ns
ns
ns
ns
ns
.