k4b2g0846b Samsung Semiconductor, Inc., k4b2g0846b Datasheet - Page 19

• Manufacturer Part Number: k4b2g0846b
• Description: 2gb B-die Ddr3 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G04(08/16)46B
9.0 AC and DC Output Measurement Levels
9.1 Single Ended AC and DC Output Levels
[ Table 14 ] Single Ended AC and DC output levels
Note : 1. The swing of +/-0.1 x V
9.2 Differential AC and DC Output Levels
[ Table 15 ] Differential AC and DC output levels
Note : 1. The swing of +/-0.2xV
9.3.Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
for single ended signals as shown in Table 16 and figure 6.
[ Table 16 ] Single Ended Output slew rate definition
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single Ended Output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals
For Ron = RZQ/7 setting
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
Single ended output slew rate
V
V
V
V
V
Symbol
OM
OH
OH
OL
OL
V
V
Symbol
OHdiff
OLdiff
(DC)
(AC)
(DC)
(DC)
(AC)
and an effective test load of 25
and an effective test load of 25
(DC)
Parameter
(AC)
Parameter
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
Parameter
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
Description
DDQ
DDQ
Symbol
SRQse
is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 40
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40
Ω
Ω
to V
to V
TT
TT
Figure 6. Single Ended Output Slew Rate definition
Min
=V
=V
2.5
DDR3-800
DDQ
DDQ
delta
/2.
/2 at each of the differential outputs.
TFse
V
V
Max
OH
From
OL
5
(AC)
(AC)
Page 19 of 61
Measured
Min
2.5
DDR3-1066
V
V
OH
OL
To
(AC)
(AC)
Max
delta
5
TRse
Min
2.5
DDR3-800/1066/1333/1600
DDR3-800/1066/1333/1600
DDR3-1333
V
V
V
OH(AC)
TT
OL(AC)
V
V
TT
TT
+0.2 x V
-0.2 x V
0.8 x V
0.5 x V
0.2 x V
+ 0.1 x V
- 0.1 x V
Max
5
2Gb DDR3 SDRAM
DDQ
DDQ
DDQ
DDQ
V
V
DDQ
Rev. 1.0 December 2008
OH
OH
DDQ
DDQ
Defined by
Delta TRse
Delta TFse
(AC)-V
(AC)-V
TBD
Min
DDR3-1600
OL
OL
(AC)
(AC)
Max
OL
5
Units
Units
(AC) and V
V
V
V
V
V
V
V
Units
V/ns
Notes
Notes
OH
1
1
1
1
(AC)
Ω
Ω