k4b2g0846b Samsung Semiconductor, Inc., k4b2g0846b Datasheet - Page 30

• Manufacturer Part Number: k4b2g0846b
• Description: 2gb B-die Ddr3 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G04(08/16)46B
[ Table 31] Basic IDD and IDDQ Measurement Conditions.
IDD0
IDD1
IDD2N
DD2NT
DDQ2NT
(optional)
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDDQ4R
(optional)
IDD4W
IDD5B
IDD6
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8
Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table32); Output Buffer and RTT: Enabled in Mode Registers
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 ; BL: 8
Bank Address Inputs, Data IO: partially toggling according to Table 33 ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table33); Output Buffer and RTT: Enabled in Mode Registers
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8
according to Table 34 ; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
Signal: stable at 0; Pattern Details: see Table 34
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8
according to Table 35 ; Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
Signal: toggling according to Table 35 ; Pattern Details: see Table 35
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8
MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
Power Down Mode: Slow Exi
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8
MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
Power Down Mode: Fast Exit
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8
MID-LEVEL; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8
according to Table 34 ; Data IO: MID-LEVEL; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
nal: stable at 0; Pattern Details: see Table 34
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8
MID-LEVEL;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8
according to Table 36 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Regis-
ters
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8
gling according to Table 37 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 37; DM: stable at 0;
Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at HIGH; Pattern Details: see Table 37
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 ; BL: 8
toggling according to Table 38 ; Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT:
Enabled in Mode Registers
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: see Table 30 ; BL: 8
Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details: see Table 36
b)
; ODT Signal: stable at 0; Pattern Details: see Table 38
c)
c)
a)
; AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Self-Refresh operation;
b)
; ODT Signal: MID-LEVEL
d)
; Self-Refresh Temperature Range (SRT): Normal
Page 30 of 61
a)
a)
a)
a)
a)
a)
a)
a)
a)
; AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially tog-
b)
b)
; ODT Signal: stable at 0; Pattern Details: see Table 32
; ODT Signal: stable at 0; Pattern Details: see Table 33
a)
; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially
a)
; AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address
a)
; AL: 0; CS: High between ACT, RD and PRE; Command, Address,
e)
; CKE: Low; External clock: Off; CK and CK:
2Gb DDR3 SDRAM
b)
b)
; ODT Signal: stable at 0
Rev. 1.0 December 2008
b)
b)
; ODT Signal: stable at 0
; ODT Signal: stable at 0; Pecharge
; ODT Signal: stable at 0; Pecharge
b)
b)
; ODT Sig-
b)
; ODT
; ODT
b)
;