ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 9

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ORCA ORT8850 Data Sheet
with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other
functions of two output signals.
The output flip-flop, in combination with output signal multiplexing, is particularly useful for registering address sig-
nals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer
signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition,
this 3-state signal can be registered or nonregistered.
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These
modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing
data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and
out of the I/O buffers on both edges of the clock.
The new Programmable I/O cell allows designers to select I/Os which meet many new communication standards
permitting the device to hook up directly without any external interface translation. They support traditional FPGA
standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-ori-
ented I/O ring architecture, designs can be implemented using 3.3V/ 2.5V/1.8V/1.5V referenced output levels.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses
with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One
PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide
high connectivity with fast software routing times and high-speed system performance.
Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be
sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast
regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can
be sourced from any I/O pin, PLLs, or the PLC logic.
The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility
translates into an improved capability to route designs at the required speeds when the I/O signals have been
locked to specific pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its MicroProcessor Interface, embedded system
bus, quad-port embedded block RAMs, universal Programmable Phase-Locked Loops, and the addition of highly
tuned networking specific phase-locked loops. These functional blocks support easy glueless system interfacing
and the capability to adjust to varying conditions in today’s high-speed networking systems.
MicroProcessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8, 16,
®
and 32-bit interfaces with optional parity to the Motorola
PowerPC MPC 860 and MPC8260 bus, it can be used for
configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize
the Series 4 embedded system bus at 66 MHz performance.
The MPI provides a system-level MicroProcessor Interface to the FPGA user-defined logic, following configuration,
through the system bus, including access to the embedded block RAM and general user-logic. The MPI supports
burst data read and write transfers, allowing short, uneven transmission of data through the interface by including
data FIFOs. Transfer accesses can be single beat (1 x 4-bytes or less), 4-beat (4 x 4-bytes), 8-beat (8 x 2-bytes), or
16-beat (16 x 1-bytes).
System Bus
An on-chip, multimaster, 32-bit system bus with 1-bit parity facilitates communication among the MPI, configuration
logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specifi-
cation Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. Mas-
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