ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 81

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Package Information
Table 34 summarizes the programmable I/O clock and power pins available to the ORT8850 devices.
Table 34. ORT8850 IO and Power Pin Summary
There are some incompatibilities between the ORT8850H and ORT8850L due to the fact that the ORT8850L is a
much smaller array and hence does not provide as many programmable IOs (PIOs). In order to allow pin-for-pin
compatible board layouts that can accommodate either device, key compatibility issues include the following:
• Unused Pins Table 35 shows a list of bonded ORT8850H PIOs that are unused in the ORT8850L. As shown in
• Shared Control Signals on I/O Registers. The ORCA Series 4 architecture shares clock and control signals
• Edge Clock Input Pins. The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are
the table, there are 19 balls that are not available in the ORT8850L, but are available in the ORT8850H. These
user I/Os should not be used if an ORT8850L will be used.
between two adjacent I/O pads. If I/O registers are used, incompatibilities may arise between ORT8850L and
ORT8850H when different clock or control signals are needed on adjacent package pins. This is because one
device may allow independent clock or control signals on these adjacent pins, while the other may force them to
be the same. There are two ways to avoid this issue.
shown in the following pinout tables under the I/O pad columns as those ending in C.
– Always keep an open bonded pin (non-bonded pins for the ORT8850L do not count) between pins that
– Place and route the design in both the ORT8850H and ORT8850L to verify both produce valid designs. Note
– 2X/4X I/O Shift Registers. If 2X I/O shift registers or 4X I/O shift registers are used in the design, this may
require different clock or control signals. Note that this open pin can be used to connect signals that do not
require the use of I/O registers to meet timing.
that this method guarantees the current design, but does not necessarily guard against issues that can
occur when design changes are made that affect I/O registers.
cause incompatibilities between the ORT880L and ORT8850H because only the A and C I/Os in a PIC sup-
port 2X I/O shift registers and only A I/Os supports 4X I/O shift register mode. A and C I/Os are shown in the
following pinout tables under the I/O pad columns as those ending in A or C.
User I/O Single Ended
User I/O Differential Pairs (LVDS, LVPECL)
Configuration
Dedicated Function
VDD15
VDD33
VDDIO
Vss
Single-Ended/Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
I/O or Power Type
81
ORT8850L
ASIC I/O
ASIC I/O
ASIC I/O
64/32
47/20
44/18
76/32
55/27
278
129
48
28
38
89
7
3
ORCA ORT8850 Data Sheet
ORT8850H
ASIC I/O
ASIC I/O
ASIC I/O
68/32
47/20
44/18
76/32
62/27
297
129
48
28
38
89
7
3