ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 50

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 16. Operating Modes and Data Paths - SONET Logic Block
All timing is referenced to the clock signal at the FPGA/Core interface. Data is also timed for signals at the
FPGA/Core interface. There will be additional time delays until the interface signals reach the capturing latch. The
primary or secondary path delay is controlled, as noted earlier, and the clock timing at the capture latch can be pre-
dicted. The data delay, however, may be unique to each interconnect routing.
The timing diagrams provide a quantitative picture of the relative importance of setup and hold margins for the
cases discussed. In the diagrams, the launch and capture times and the time difference between the launching and
capturing clock edges are identified. As the time between launch and capture increases (up to a full clock period),
the possibility of a setup time problem decreases. Also, the possibility of a setup time problem decreases for
smaller maximum propagation delay values.
If capture occurs before the next data is launched, a hold time problem cannot occur. In nearly all cases, the differ-
ence between the launch and capture clock edges will be nearly a full clock cycle and the data will be captured
before the next data is launched. This is not guaranteed, however, and ispLEVER timing analysis should be done
for each application.
The general rules used for the FPGA/Core interface are as follows:
1. If possible, transfers across the FPGA/Core interface should be direct register to register transfers with minimal
2. Use positive (rising) edge flip-flops in the FPGA for both input and output unless a timing diagram (case 1)
3. Attempt to ‘locate’ the FPGA side flip-flops reasonably close to the interface unless other timing constraints
4. Pay attention to the clock routing resource recommended (these are fixed on the ORT8850), and to the delay
5. Run Trace setup and hold checks in ispLEVER on the routed design taking the environmental constraints into
For the cases where parallel data is output from the core, the reference clock is also output from the core and the
effects of propagation delay variation are included in the discussion. Propagation delay is defined relative to the
interface signals and thus is the time from the enabling (falling) edge of the clock from the core to the time that data
is guaranteed to be valid at the interface. As an example, for the first case discussed, the minimum (tprop_min) and
maximum (tprop_max) propagation delays are 0.8 ns. and 4.7 ns. respectively. Therefore the data outputs are sta-
ble for 6.1 ns. (10 ns. - 3.9 ns.) of each clock cycle. The data must be captured during this stable period, i.e., the
data signals must arrive at the capturing latch with adequate setup and hold margins versus the clock signal at the
latch.
In the first case, Figure 27, the alignment FIFO is assumed to be bypassed and all timing is with respect to the
recovered clock. The FPGA is latched on the falling edge of the clock, an exception to the general recommenda-
Case
or preferably no intervening logic.
explicitly indicates otherwise, or a special case (long routing path, etc.) is being considered.
prevent this. This ‘locate’ is typically achieved by placing a frequency constraint on the FPGA_CLK signal. In
most cases, up the 3 ns of data path delay through the FPGA logic in the ORT8850 is acceptable.
and skew limits and the clock source points.
account. (See ispLEVER Application Note for details).
1
2
3
4
5
DOUTxx[7:0]
DOUTxx[7:0]
DINxx[7:0]
TOH_OUTxx
TOH_INxx
Data (Note: xx
=[AA, …BD])
Core to FPGA
Core to FPGA
FPGA to Core
Core to FPGA
FPGA to Core
Data Path
Embedded Core
Launch/Latch
Falling Edge
Falling Edge
Falling Edge
Rising Edge
Rising Edge
Clock
50
Launch/Latch
FPGA Clock
Falling Edge
Rising Edge
Rising Edge
Rising Edge
Rising Edge
ORCA ORT8850 Data Sheet
CDR_CLK_xx/Secondary
FPGA_SYSCLK/Primary
FPGA_SYSCLK/Primary
From FPGA/Secondary
From FPGA/Secondary
Clock/Route