ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 39

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 20. Alignment of all Eight SERDES Channels.
There is a provision to allow certain streams to be disabled (i.e. not producing alarms or affecting synchronization).
These streams can be enabled at a later time without disrupting other streams. If the newly enabled stream needs
to be a part of a bigger group the entire group must be resynchronized unless the affected stream was active when
the initial synchronization was performed. As long as all streams to be aligned were active when the most recent
synchronization was performed, individual streams may be enabled or disabled without affecting synchronization.
It is recommended that users select the smallest possible groups for channel alignment. If an application only
requires that two channels be aligned then it is best to use by-2 grouping. All of the channels in a group will affect
the group’s total alignment. If a channel in a group fails or is shut down it will not affect any of the other channels in
the group. This channel will simply be removed from the alignment algorithm. When the channel is re-enabled into
a working group it will be out of alignment with the rest of the group. It will be necessary to perform a FIFO realign-
ment procedure to realign the group. During a FIFO realignment data will not pass through any of the channels in
the alignment group.
Alignment FIFO Algorithm
The algorithm controlling writes to the alignment FIFO and reads from it operates as follows: Prior to detecting the
first frame pulse for a link being aligned, each link in the group continually writes to address 0 within its own FIFO
(each link has a FIFO). When the first link in the group receives a frame pulse from Framer block the write pointer
for the corresponding FIFO increments to next write address on each clock cycle. L inks that have not received a
frame pulse continue to write into their respective FIFOs. When any link receives a frame pulse, the write address
for that FIFO will be reset to ‘0’
The operation of the alignment algorithm requires a wait of several clocks from the first arriving frame pulse before
reading of FIFO data begins. In this case, when all frame pulses arrive together the alignment algorithm initiates
reads after 9 clocks cycles. If, however, the first to last arriving frame pulses are separated by multiple clock cycles,
there will be additional clock cycles between the first frame pulse and the first read. If all links in the group have not
reported a valid frame pulse signal after 18 clock cycles, an out of sync state is entered and an alarm is generated.
After all links have received frame pulses and are incrementing their write addresses while writing into their FIFOs,
data is then read out of each link's FIFO one byte at a time. All aligned links are now Frame/byte/bit synchronous.
FIFO Alignment Procedure
The FIFO alignment block has the ability to be realigned by changing the value of bits in the alignment control reg-
isters. This may be done in the FPGA logic or under the control of an external device through the system bus or
MPI. Alignment must take place after the stream has settled with valid data to guarantee proper channel alignment
and uncorrupted data transmission.
Channel realignment must occur when a channel goes from the Out-Of-Frame (OOF) state to the In-Frame state.
This happens when the channels are first powered up and given a valid frame pulse. This is the obvious known
Channel BA
Channel BD
Channel AB
Channel AA
Channel BB
Channel AD
Channel BC
Channel AC
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Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
ORCA ORT8850 Data Sheet
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