ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 54

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
The next two examples show timing for serial TOH data input and output. For these cases, the clock is generated in
the FPGA logic and the discussion accounts for the skew between the clock signal at the FPGA latch and at the
FPGA/Core interface. The clock is routed over a secondary clock path and the skew can vary by ± 3 ns. A value of
+ 2 ns was assumed in the discussions.
Figure 30 shows the timing for sending serial TOH data from the Core to the FPGA logic with data being launched
and latched on the same (rising) clock edge. As in the previous examples, setup and hold time constraints for the
data versus the reference clock at the capturing latch must be met. Data is not captured before the next data is
launched, so there might be a hold time margin problem. Launched data has nearly a full clock period to become
stable at the capture latch and the maximum propagation delay is only 0.2 ns so setup margin should not be a
problem for the timing relationships assumed. Actual timing analysis should be performed for each application
because of the wide range of possible skew values.
Figure 30. Full Cycle, TOH Output Configuration and Timing (-1 Speed Grade)
a. Configuration
b. Timing (ns)
FPGA_CLK
FPGA
Logic
tprop_min = - 0.5
ASB_TOH_CLK
TOH_OUTxx
FPGA_CLK
TOH_CLK
+2.0 ns assumed
Secondary Clock
±3.0 ns skew
+
D
0.0
0.4
Launch
2.0
Δt
tprop_max = 2.0
Note: xx - [AA, AB, ..., BD]
4.7
5.1
TOH_OUTxx
Data Valid
TOH_CLK
54
6.7
Capture
9.4
8.8
Δ t
0.4 ns
11.4
Hold
14.5
14.1
Q
ORCA ORT8850 Data Sheet
16.1
+
18.8
ASB_TOH_CLK
19.2
Embedded
Core