ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 35

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 16. Basic Logic Blocks, Receive Path, Single Channel
HSI Functions (Clock Recovery and Deserializer)
The HSI receive path functions include Clock and Data Recovery (CDR) and deserialization of the incoming data
from the selected work or protect input stream to the byte-wide internal data bus format. The serial data received
from the LVDS buffer does not have an accompanying clock. Based on data transitions, the receiver selects an
appropriate internal clock phase for each channel to retime the data. The retimed data and clock are then passed
to the DEMUX (deserializer) module. The DEMUX module performs serial-to-parallel conversion and provides par-
allel data and clock to the SONET framer block. For a 622 Mbits/s SONET stream, the HSI will perform Clock and
Data Recovery (CDR) and MUX/DEMUX between 77.76 MHz byte-wide internal data buses and 622 Mbits/s serial
LVDS links.
Sampler
This block operates on the byte-wide data directly from the HSI macro. The HSI external interface always runs at
622 Mbits/s (STS-12), or 850 Mbits/s, but it can be connected directly to a 155 Mbits/s STS-3 stream. If connected
to a 155 Mbits/s stream, each incoming bit is received four times. This block is used to return the byte stream to the
expected STS-12 format. The mode of operation is controlled by a register and can either be STS-12 (pass-
through) or STS-3. The output from this block is not bit aligned (i.e., an 8-bit sample does not necessarily contain
an entire SONET byte), but it is in standard SONET STS-12 format (i.e., four STS-3s) and is suitable for framing.
SONET Framer Block
The framer block takes byte-wide data from the HSI, and outputs a byte-aligned, byte-wide data stream and 8 kHz
sync pulse. The framer algorithm determines the out-of-frame/in-frame status of the incoming data and will set
alarm register bits on both an errored frame and an Out-Of-Frame (OOF) state.
The framer block takes byte wide data from the HSI, and outputs a byte aligned byte wide stream and 8 kHz sync
pulse asserted coincident the first A1 byte which will be used by following blocks. (Note however that if the pointer
RX_TOH_CK_EN
TOH_CK_LP_EN
FPGA_SYSCLK
DOUTxx_C1J1
DOUTxx_PAR
DOUTxx_SPE
CDR_CLK_xx
DOUTxx[7:0]
TOH_OUTxx
DOUTxx_EN
RX_TOH_FP
DOUTxx _FP
TOH_xx_EN
FPGA
Logic
TOH_CLK
LINE_FP
SYS_FP
2
*
MUX
Parity
Gen.
MUX
Bypass Align*
Bypass Mover*
Pointer
Mover
Bypass Align*
(opt.)
MUX
Line Lbk.*
TOH Data
Parallel to
Convert
Control
Serial
TOH
Port
2
Insert Bus
Par. Err.*
K1/K2 Pass
/Regen*
STS 12/48*
Control and
TOH Clock
Control
Control and
TOH Clock
7 channels
FIFO
Align.
W/R
FIFO
(opt.)
To other
Min/Max Th.*
3
FP
Sync.
S
FIFO
Insert
AIS
FIFO
Control
2
Insert AIS-L*
Insert AIS-L
on LOF*
B1 Check
LOF
FIFO
Control
Old B1
(opt.)
Read
(opt.)
SONET Logic
Scrambler
Prev.
B1
(opt.)
De-
Embedded Core
35
Logic Common
to Both Quads
New B1
Calc.
FP
F
Framer
Notes: n=[7,…0]
(opt.)
xx=[AA, AB,…BD]
Recovered 77.76 MHz
* ~ Signal from Control
FP
FP
LOF~ Loss of Frame
Sampler
STS3)
(for
7 channels
F
S
To other
Register
~ Framer Frame Pulse
~ FIFO Sync Frame Pulse
Parallel
Serial
77.76 MHz
To
ORCA ORT8850 Data Sheet
CDR
Buffers
MUXs
LVDS
MUX
LVDS
Buffer
And
I/O
SYS_CLK_[P:N]
RXDxx_W_[P:N]
RXDxx_P_[P:N]
Backplane
2
2
2
Serial
Link