ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 59

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Table 19. Memory Map Descriptions (Continued)
Lattice Semiconductor
Absolute
Address
3000A
3000B
30009
(0x)
[0:4]
[5-7]
[0:4]
[5-7]
Bit
[0]
[3]
[4]
[5]
[6]
[7]
[1]
[2]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
TOH serial port
output MUX select
for AA/AB
TOH serial port
output MUX select
AC/AD
DOUT parallel port
output MUX select
for AA/AB
DOUT parallel port
output MUX select
for AC/AD
TOH serial port
output MUX select
for BA/BB
TOH serial port
output MUX select
for BC/BD
DOUT parallel port
output MUX select
for BA/BB
DOUT parallel port
output MUX select
BC/BD
FIFO aligner
threshold value
(min)
Not Used
FIFO aligner
threshold value
(max)
Not Used
Name
decimal
decimal
Reset
Value
(0x)
N/A
N/A
40
A8
15
1
1
1
1
1
1
1
1
2
59
0 = AB TOH is output on AA
1 = AA TOH is output on AA
0 = AD TOH is output on AC
1 = AC TOH is output on AC
0 = AB data is output on AA
1 = AA data is output on AA
0 = AD data is output on AC
1 = AC data is output on AC
0 = BB TOH is output on BA
1 = BA TOH is output on BA
0 = BD TOH is output on BC
1 = BC TOH is output on BC
0 = BB data is output on BA
1 = BA data is output on BA
0 = BD data is output on BC
1 = BC data is output on BC
Minimum threshold value for the per channel receive direction
alignment FIFOs. If and when the minimum threshold value is
violated by a particular channel, then the “FIFO aligner thresh-
old error” alarm bit will be generated for that channel and if
enabled, latched as a “FIFO aligner threshold error flag” in the
respective channel alarm register.
The allowable range for minimum threshold values is 1 to 23.
Note that the minimum FIFO aligner threshold value applies to
all eight channels.
MSB bit is 4.
The allowable range for maximum threshold values is 0 to 22.
MSB bit is 4
ORCA ORT8850 Data Sheet
Description