ort8850 Lattice Semiconductor Corp., ort8850 Datasheet - Page 57

• Manufacturer Part Number: ort8850
• Description: Field-programmable System Chip Fpsc Eight-channel X 850 Mbits/s Backplane Transceiver
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 18. LVDS Protection Switching (Continued)
For software control of the LVDS protection switching there is an enable bit to enable software control, and a bit per
channel which selects main or protect. The enable register is at 0x30008 in the memory map (Table 19).
Memory Map
The memory map for the ORT8850 core is only part of the full memory map of the ORT8850 device. The ORT8850
is an ORCA Series4 based device and thus uses the system bus as a communication bridge. The ORT8850 core
register map contained in this data sheet only covers the embedded ASIC core of the device, not the entire device.
The system bus itself, and the generic FPGA memory map, are fully documented in the MPI/System Bus Applica-
tion Note. As part of the system bus, the embedded ASIC core of an FPSC is located at address offset 0x30000.
The ORT8850 embedded core is an eight-bit slave interface on the Series 4 system bus.
Each ORCA device contains a device ID. This device ID is unique to each ORCA device and can be used for device
identification and assist in system debugging. The device ID is located at absolute address 0x00000 - 0x00003.
The ORT8850H’s device ID is 0xDC0123C0 and the ORT8850L’s device ID is 0xDC0121C0. More information on
the device ID and other Series 4 generic registers can be found in the MPI/System Bus Application Note.
The ORT8850 core registers are clocked by the reference clock SYS_CLK_P/N. If a clock is not provided to the ref-
erence clock, the registers will fail to operate.
The ORT8850 core registers do not check for parity on a write operation. On a read operation, no parity is gener-
ated, and a “0” is passed back to the initiating bus master interface on the parity signal line.
Registers Access and General Description
The memory map comprises three address blocks:
• Generic register block: ID, revision, scratch pad, lock and reset register.
• Device register block: control and status bits, common to the eight channels in each of the two quad interfaces.
• Channel register blocks: each of the four channels in both quads have an address block. The four address blocks
All registers are write-protected by the lock register, except for the scratch pad register. The lock register is a 16-bit
read/write register. Write access is given to registers only when the key value 0x0580 is present in the lock register.
An error flag will be set upon detecting a write access when write permission is denied. The default value is
0x0000.
After power-up reset or soft reset, unused register bits will be read as zeros. Unused address locations are also
read as zeros. Bit in write-only registers will always be read as zeros.
This table is constructed to show the correct values when read and written via the system bus MPI interface. When
using this table while interfacing with the system bus user logic master interface, the data values will need
to be byte flipped. This is due to the opposite orientation of the MPI and master interface bus ordering. More infor-
mation on this can be found in the MPI/System Bus Application Note (TN1017).
in both quads have the same structure, with a constant address offset between channel register blocks.
FPGA Interface Signal
LVDS_PROT_BA
LVDS_PROT_BB
LVDS_PROT_BC
LVDS_PROT_BD
Channel BC gets TXD_BC_W_[P:N]
Channel BD gets TXD_BD_W_[P:N]
Channel BA gets TXD_BA_W_[P:N]
Channel BB gets TXD_BB_W_[P:N]
When ‘0’
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ORCA ORT8850 Data Sheet
Channel BC gets TXD_BC_P_[P:N]
Channel BD gets TXD_BD_P_[P:N]
Channel BA gets TXD_BA_P_[P:N]
Channel BB gets TXD_BB_P_[P:N]
When ‘1’