r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 96

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.17 Pipe Control Register
Remarks
None
R e v 1 . 0 1
4-2 Unassigned. Fix to "0".
1-0
Bit
15
14
13
12
11 Unassigned. Fix to "0".
10
9
8
7
6
5
♦ Pipe1 control register [PIPE1CTR]
♦ Pipe2 control register [PIPE2CTR]
♦ Pipe3 control register [PIPE3CTR]
♦ Pipe4 control register [PIPE4CTR]
♦ Pipe5 control register [PIPE5CTR]
BSTS
BSTS
Buffer status
INBUFM
Sending buffer
monitor
CSCLR
CSPLIT status clear
bit
CSSTS
CSSTS status bit
ATREPM
Auto response mode
ACLRM
Auto
mode
SQCLR
Toggle bit clear
SQSET
Toggle bit set
SQMON
Toggle bit confirm
PBUSY
Pipe busy
PID
Response PID
15
0
-
INBUFM
O c t 1 7 , 2 0 0 8
Name
buffer
14
0
-
CSSLR CSSTS
13
clear
0
-
The FIFO buffer status of the pipe is shown.
0: Buffer access is disabled
1: Buffer access is enabled
When the pipe is transmitting, the FIFO buffer status of the pipe
is shown.
0: FIFO buffer contains no transmittable data
1: FIFO buffer contains transmittable data
Write CSCLR=1 to clear the CSSTS bit of the pipe.
0: Write invalid
1: Clear CSSTS bit
C-Split status of split transaction of the pipe is shown.
0: During the S-Split transaction process or transfer without using
a split transaction
1: During the C-Split transaction process
Specifies auto response is disabled/enabled for the pipe.
0: disabled
1: enabled (irrespective of the FIFO buffer status of the pipe, a
zero-length packet response while sending, NAK response and a
NRDY interrupt is issued while receiving)
Specifies auto buffer clear mode is disabled/enabled of the pipe.
0: Disabled
1: Enabled (all buffers are initialized)
Specifies "1" while clearing the expected value of the sequence
toggle bit in the next transaction of the pipe, to DATA0.
0: Write invalid
1: Specifies DATA0
Specifies "1" while clearing the expected value of the sequence
toggle bit in the next transaction of the pipe, to DATA1.
0: Write iis nvalid
1: Specifies DATA1
Sets the expected value of the sequence toggle bit in the next
transaction of the pipe.
0: DATA0
1: DATA1
Sets whether the pipe is being used by the current USB bus.
0: Pipe not used in the USB bus
1: Pipe used in the USB bus
Specifies the response method in the next transaction of the
pipe.
00: NAK response
01: BUF response (maintaining the buffer state)
10: STALL response
11: STALL response
12
0
-
p a g e 9 6 o f 1 8 3
11
?
?
ATREPM
10
0
-
ACLRM SQCLR SQSET
9
0
-
Function
8
0
-
7
0
-
SQMON
6
0
-
PBSY
5
0
-
4
?
?
R(0)/W(1)
R(0)/W(1)
Software
R/W(1)
R/W
R/W
R/W
R
R
R
R
R
3
?
?
<Address: 70H>
<Address: 72H>
<Address: 74H>
<Address: 76H>
<Address: 78H>
Hardware Remarks
2
R/W(0)
?
?
R/W
R/W
W
W
W
W
R
R
R
R
1
0
0
(Set to "0"
(Set to "0"
PID
when H)
when P)
H
H
P
0
0
0