r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 57

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.11.9 Port0 OVRCR Interrupt status bit (OVRCR)
2.11.10 Port0 USB bus change interrupt status bit (BCHG)
2.11.11 Port0 USB detach detection interrupt status bit for the Host Controller function (DTCH)
2.11.12 Port0 USB attach detection interrupt status bit for the Host Controller function (ATTCH)
R e v 1 . 0 1
When input status of the OVCUR0A or OVCUR0B pin is modified (from Low to High, or from High to Low), this
controller detects the Port0 OVRCR interrupt and sets "1" to this bit. Here, if "1" has been written to the applicable
interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that the interrupt is issued. This
controller shows the present input status for the OVCUR0A and OVCUR0B pins in the SYSSTS0 register OVCMON
bit.
When selecting the Host Controller function, it is possible to detect the occurrence of the software over-current if the
over-current notification signal from the power supply IC, which supplies the VBUS for the devices to be connected to
the USB on Port0, is written to the OVCUR0A or OVCUR0B pin. When the OVRCR interrupt is issued, use the
software several times to check the consistency in read of the OVCMON bit and reject the chattering.
When a state change for Full-/Low-Speed signal level of Port0 is issued (modify from J-State, K-State, or SE0 State to
J-State, K-State or SE0 State), this controller detects the Port0 BCHG interrupt and sets "1" to this bit. Here, if "1" has
been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies
that the interrupt is issued. This controller displays the present input status of Port0 in the SYSSTS0 register LNST bit.
Enable the BCHG interrupt under the following conditions:
When a BCHG interrupt occurs in condition (1), confirm the remote wakeup of the Peripheral Device with the
DVSTCTR register RESUME bit. When a BCHG interrupt occurs under conditions (2) or (3), eliminate chattering on the
LNST bit with software, and check for attach/detach to/from the Peripheral Device.
When the USB bus detach for Port0 is detected, this controller detects the Port0 DTCH interrupt and sets "1" to this bit.
Here, if "1" has been written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N
pin and notifies that the interrupt is issued.
This controller detects the bus detach using the standards as given in the USB Specification Revision 2.0.
This controller controls the hardware given below after detecting the DTCH interrupt (irrespective of the setting value of
the applicable interrupt permitted bit). The software closes all communication by the pipe for all applicable ports. Then,
modify the status to attach wait (issue ATTCH interrupt) for the applicable ports.
(1) Modify the UACT bit of the port where the DTCH interrupt has been detected to "0" and set.
(2) Modify the status of the port where the DTCH interrupt was issued to "idle".
When selecting the Host Controller function, and when this controller detects the J-State or K-State of Full-/Low-Speed
signal level on Port0 within 2.5µs, it detects the Port0 ATTCH interrupt and sets "1" to this bit. Here, if "1" has been
written to the applicable interrupt permitted bit by the software, this controller asserts the INT_N pin and notifies that
the interrupt is issued.
The specific ATTCH interrupt detection conditions for this controller are given below:
(1) When modified from K-State, SE0 or SE1 to J-State and continued in the J-State for 2.5µs
(2) When modified from J-State, SE0 or SE1 to K-State and continued in the K-State for 2.5µs
(1) When enabling remote wakeup to enter the suspend status
(2) When stopping the clock to enter the suspend status (necessary in order to detect detach during suspend
(3) . When clock is stopped because no Peripheral Devices is connected (necessary to detect attach)
O c t 1 7 , 2 0 0 8
status)
p a g e 5 7 o f 1 8 3