r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 80

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.15.9 C-SPLIT status clear bit of split transaction (CSCLR)
2.15.10 C-SPLIT status bit of split transaction (CSSTS)
2.15.11 SUREQ clear bit (SUREQCLR)
2.15.12 Clear bit of sequence toggle bit (SQCLR)
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When the Host Controller function is selected, if the software writes "1" to this bit, the controller clears the CSSTS bit to
"0". In transfer using Split Transaction, to restart the next transfer forcefully from S-Split, write "1" to this bit. In normal
Split Transactions, since the controller clears the CSSTS bit automatically to "0" when the C-Split ends, the clear
process by the software is not required.
Control the CSSTS bit by using it when the communication is stopped by "UACT=0" or when it is confirmed that
transfer is not complete due to detach detection.
When "CSSTS=0", it remains "CSSTS=0" even if "1" is written to this bit.
When the Peripheral Controller function is selected, write "0" to this bit.
When the Host Controller function is selected, the controller sets the C-Split status of the split transaction to this bit.
The controller sets "1" to this bit while starting the C-Split, and sets "0" when the C-Split end is detected.
Setting this bit sets a valid value only when the Host Controller function is selected.
When the Host Controller function is selected, if the software writes "1" to this bit, the controller clears the SUREQ bit
to "0". The controller always sets this bit to "0". In the Setup transaction, when communication is stopped by writing
"SUREQ=1" without modifications, use the software to write "1" to this bit. In the usual Setup transaction, since the
controller clears the SUREQ bit automatically to "0" when the transaction ends, the clear process by the software is not
required.
Control the SUREQ bit by using this bit when the communication is stopped by "UACT=0", or when it is confirmed that
transfer is not complete due to detach detection.
When the Peripheral Controller function is selected, write "0" to this bit.
If the software writes "1" to this bit, the controller writes the expected value of the sequence toggle bit of the pipe to
DATA0. The controller always sets "0" to this bit. Do not write "1" to the SQCLR bit and SQSET bit simultaneously.
Write "1" to this bit when "CSCTS=0", "PID=NAK" and "when not set to CURPIPE".
To write "1" to this bit after modifying the PID bit of the corresponding pipe from "BUF" to "NAK", check that
"CSSTS=0" and "PBUSY=0", and then write the bit. However, since the controller has modified the PID bit to "NAK", it
is not necessary to check the PBUSY bit.
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