r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 182

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
4.11.6 DMA access timing (burst transfer, when a multiplex bus is set)
4.11.6.1 DMA burst transfer write timing (CPU multiplex bus setting: DFORM=000)
4.11.6.2 DMA burst transfer read timing (CPU multiplex bus setting: DFORM=000)
Note 6-1: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N.
Note 6-2: The control signal when reading data is a combination of CS_N and RD_N.
Note 6-3: RD_N, WR0_N and WR1_N should not be timed to fall when CS_N is rising. Similarly, CS_N should not be timed to
fall when RD_N or WR0_N and WR1_N are rising. In the instances noted above, an interval of at least 10ns must be left open.
Note 6-4 : When the receipt data is one byte, the DEND determined time is "(24)td(DREQ-DendV)".
Note 6-5:The time required until DREQi_N (i=0,1) becomes active is valid, when the next DMA transfer exists, and when tdis
(CTRL-Dreq) or tdis (PCTRLH - Dreq) has slow ratings.
R e v 1 . 0 1
AD6-AD1 /
DREQi_N
DENDi_N
WR0_N,
WR1_N
D15-D0
AD6-AD1 /
(i=0, 1)
(i=0, 1)
Note 6-3
Note 6-1
DREQi_N
DENDi_N
CS_N
Note 6-3
O c t 1 7 , 2 0 0 8
D15-D0
ALE
Note 6-4
(i=0, 1)
(i=0, 1)
RD_N
CS_N
Note 6-2
ALE
tsu (A - ALE)
36
32
tw (ALE)
48
tw (CTRL_B)
tsu (A - ALE) th (A - ALE)
tw (ALE)
32
36
tw (CTRL_B)
48
Address
p a g e 1 8 2 o f 1 8 3
Address
tdwr (ALE_CTRL)
thw (A - ALE)
tdwr (ALE_CTRL)
tw (cycle1)
tw (cycle1)
D0
11
trec (CTRL_B)
D0
35
ta (CTRL - DendV)
trec (CTRL_B)
35
37
Address
47-1
Address
37
43
47-1
3
tsu (D) th (D)
49
ta (CTRL-D)
D1
49
D1
tv (CTRL - DendV)
44
tv (CTRL-D)
25
18
17
tdis (PCTRLH - Dreq) Note 6-5
17
Address
45
Address
tdis (CTRL - Dreq)
tdis (CTRLH - Dreq)
4
tdis (CTRL - Dreq)
tsu (DEND) th (DEND)
12
Dn
Dn
46