r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 165

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
4.8 Switching Characteristic (VIF = 2.7~3.6V, or 1.6~2.0V)
Key:
R e v 1 . 0 1
tdis (PCTRLH - Dreq)
tdis (CTRLH –Dreq)
ten (CTRL – Dend)
tdis (CTRL – Dreq)
ta (CTRL - DendV)
tv (CTRL - DendV)
ten (CTRL – Dreq)
td (Dreq - DendV)
tv (CTRL – Dend)
tdis (CTRL-Dend)
ta (CTRL - Dend)
td (DREQ - DV)
tv (CTRL – DV)
td (CTRL - INT)
tdis (CTRL - D)
ta (CTRL - DV)
ten (CTRL - D)
ta (CTRL - D)
tv (CTRL - D)
twh (Dreq)
twh (INT)
Symbol
ta (A)
tv (A)
ta: Access time, tv: Valid time, ten: Output enabled time, tdis: Output disabled time,
(A): Address, (D): Data, (Dend): DiEND_N, (Dreq): DiREQ_N, (CTRL): Control, (V): Obus=0
O c t 1 7 , 2 0 0 8
Time that DREQ is disabled after writing in
Time that DEND output can be accessed
Time that DEND output can be accessed
Time that DREQ is disabled after control
(DMA Interface) Obus=0 or CPU BUS1, 2
asserted when split bus (DMA Interface)
Time that DREQ is enabled after control
Time that DREQ is disabled after end of
Time that DEND output is disabled after
when split bus (DMA Interface) Obus=0
Time that DEND output is enabled after
DEND input is completed and control is
Time that data can is valid after control
control when split bus (DMA Interface)
Time that data output is disabled after
DEND output determination time after
Time that data output is enabled after
Data access after DREQ begins to be
Time that data can be accessed after
Time that data can be accessed after
Time that DEND output is valid after
Time that DEND output is valid after
starting DREQ assert, when Split bus
Time that data is valid after address
control when CPU bus and split bus
control when CPU bus and split bus
control when CPU bus and split bus
control when CPU bus and split bus
Time that data is valid after control
after control when split bus (DMA
after control when split bus (DMA
p a g e 1 6 5 o f 1 8 3
INT output negated delay time
DREQ output "H" pulse width
INT output "H" pulse width
(DMA Interface) Obus=0
(DMA Interface) Obus=1
(DMA Interface) Obus=1
(DMA Interface) Obus=1
Address access time
Interface) Obus=0
Interface) Obus=1
previous control
completed
Obus=0
Obus=0
control
control
control
Item
CL=50pF
CL=10pF
CL=50pF
CL=10pF
CL=50pF
CL=30pF
CL=10pF
CL=30pF
CL=10pF
CL=30pF
CL=10pF
CL=30pF
650
20
20
2
2
2
2
2
2
2
Rated value
250
30
30
30
30
30
30
30
30
30
70
50
70
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
9