r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 139

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
3.4.3
3.4.3.1 DMA Transfer Outline
3.4.3.2 DMA Control Signal Selection
R e v 1 . 0 1
DREQ
DACK
RD/W R
CS
ADDR
D15-0
DEND
DREQ
DACK
CPU bus 0
CPU bus 1
CPU bus 2
CPU bus 3
SPLIT bus
SD7-0
DEND
*1)
CPU bus 1 DMA transfer
SPLIT bus DMA transfer
DMA Transfer (DxFIFO Port)
Pipes 1-9 can be used for FIFO port access with DMAC. When access becomes enabled for the pipe set by DMA, the
DREQ signal is asserted.
The DMA transfer can be executed in the cycle steal transfer mode, which asserts the DREQ signal every time one
data (8-bit or 16-bit) is transferred, or in the burst transfer mode, in which the DREQ signal is continually asserted until
all data transfers in the buffer memory are completed. The timing is described in detail in “Chapter 4. Electric
Characteristics.”
Select the FIFO port transfer unit (8 bits or 16 bits) with the DxFIFOSEL register MBW bit and the DMA transfer pipe
with the CURPIPE bit. Note that the pipe (value set in CURPIPE bit) should not be changed during a DMA transfer.
Select the pin for DMA transfers in the DMAxCFG register DFORM bit and control the DREQx_N pin with the
DxFIFOSEL register DREQE bit. Table 3.17provides the list of DMA control pins and Figure 3.16 shows the FIFO port
access method and the DMA control pin.
Method
Access
When setting this access method, set the CS_N to inactive (fix to “High”) while accessing the DxFIFO port.
O c t 1 7 , 2 0 0 8
DREQE
0
1
1
1
1
Register
0
0
0
0
1
p a g e 1 3 9 o f 1 8 3
DFORM
Figure 3.16 FIFO Port Access and DMA Control Pin
0
0
1
1
1
0
0
0
1
0
Table 3.17 DMA Control Pin List
DATA Bus
SPLIT
CPU
CPU
CPU
CPU
DREQ
○
○
○
○
-
DACK
Pin
○
○
○
-
-
CPU bus 2 DMA transfer
RD/WR
○
○
○
-
-
ADDR
+CS
*1)
*1)
○
○
-
CPU access
DMA through CPU bus
DMA through CPU bus
DMA through CPU bus
SPLIT bus
Reference