r8a66597 Renesas Electronics Corporation., r8a66597 Datasheet - Page 42

• Manufacturer Part Number: r8a66597
• Description: Assp Usb2.0 2 Port Host/1 Port Peripheral Controller
• Manufacturer: Renesas Electronics Corporation.

R8A66597FP/DFP/BG
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
R e v 1 . 0 1
Read count mode (RCNT)
When "0" is written to this bit, if all reception data of the FIFO buffer assigned to the pipe specified in the CURPIPE bit
is read (when the data is read on one side of a double buffer), the controller clears the CFIFOCTR register DTLN bit to
"0".
When "1" is written to this bit, the controller counts the CFIFOCTR register DTLN bit whenever the data received from
the FIFO buffer assigned to the specified bit is read.
Buffer pointer rewind (REW)
When the the specified pipe is receiving, if "1" is written to this bit during the FIFO buffer read, the initial data of the
FIFO buffer can be read (for a double buffer, the initial data on one side can be read again during the read process).
When the software writes "1" to this bit, the controller again writes "0" to this bit.
Do not modify the "REW=1" and CURPIPE bit settings at the same time. First confirm that "FRDY=1" and then write
"REW=1".
Use the BLCR bit while rewriting the initial data of the FIFO buffer for the transmission pipe.
CFIFO Port access bit width (MBW)
Control bit of CFIFO port byte endian (BIGEND)
In this bit, write the CFIFO port byte endian. Refer to 2.8.2 for details.
FIFO port access direction specification bit when selecting DCP (ISEL)
FIFO port access byte specification bit (CURPIPE)
Write the pipe number for the data to be read or written through the CFIFO port. When modifying this bit, first write the
data and then read it. Check that the written values and the read values match, and then proceed to the next process.
Do not write to the same pipe to CURPIPE of CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers.
When the settings of this bit are modified during access to the FIFO buffer, access up to then is saved. Access to the
buffer can be continued after rewriting the settings.
In this bit, set the CFIFO port access bit width.
When the pipe specified in the CURPIPE bit is receiving, if read is started after writing "1" to this bit, modify the MBW
bit from "1" to "0" only after all the data is read. When the DTLN bit is an odd number, write "MBW=0" and read with
the variable having an 8-bit length, or read with a 16-bit maintaining "MBW=1", delete the excess byte, and then read
the last byte.
When the specified pipe is receiving, set the CURPIPE bit and MBW bit simultaneously.
When the the specified pipe is transmitting, to start writing the data having an odd number of bytes by writing "1" to this
bit, write "MBW=0" and write with the variable having a 16-bit length (refer to 2.8.2 for the data to be written), or write
with the variable having an 8-bit length maintaining "MBW=1", and then write the last byte (write with the WR0_N
strobe if "BIGEND=0", and with the WR1_N strobe if "BIGEND=1").
To change this bit when the specified pipe is DCP, first write the data to this bit and then read it. Proceed to the next
process after checking if the written values match with the read values.
When the settings of this bit are modified during access to the FIFO buffer, access up to then is saved. Access to the
buffer can be continued after rewriting the settings.
Write to this bit and the CURPIPE bit simultaneously.
O c t 1 7 , 2 0 0 8
p a g e 4 2 o f 1 8 3